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I'm working on integrating an eMMC ship to a FPGA. As for now, the initialization is working fine, I've managed to receive the CSD and CID registers properly, and I can select and move the chip to Transfer State.

The way my design is built, I have to send data to the FPGA from the MCU, that can then be forwarded for programming into the eMMC.

Design principle

My question is, how am I supposed to do that properly, what is the good design pattern for this? Some kind of buffered FIFO? The MCU/FPGA communication being serial, in order to have a full byte to send I need 8 SPI clock cycles, while I need only 1 MMC's clock cycle to send it to the MMC, its link being parallel. And I can't make the MMC wait for the next byte to be ready, otherwise I'll just be programming the previously set bits for the amount of mmc's clock cycles needed for the next byte to be received.

The FPGA clock is 12MHz, SPI's is 1.5MHz, MMC's is tuneable up to 12MHz. A full block of data is 512 bytes, that's a logic vector of 4096 bits that I'm guessing I shouldn't allocate as a buffer, right?

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    \$\begingroup\$ Yes, you'd want some sort of byte-orientated fifo, preferably in a block RAM in the FPGA. Then only start the transfer to emmc once the fifo is part-full. \$\endgroup\$ – pjc50 Jul 15 '16 at 13:11
  • \$\begingroup\$ Ok, it makes sense. Any example of such implementation? Does the synthesis tool detects those kind of behavior and use the RAM blocks automatically? \$\endgroup\$ – Fluffy Jul 15 '16 at 13:22
  • \$\begingroup\$ Have a look in the usual places such as opencores for examples. Usually the tool will infer a block ram, but it may require hints - consult its documentation. \$\endgroup\$ – pjc50 Jul 15 '16 at 13:39
  • \$\begingroup\$ Ok I think I've got a working FIFO module. The thing that still troubles me, is how can I be sure that the FIFO's output won't be out-speeding the input? Can I be sure that I'll be able to send data continuously? Even if I buffer a whole 512 bytes data array, I'll empty it faster than I fill it and it'll get slow again, eventually. Am I missing something? \$\endgroup\$ – Fluffy Jul 18 '16 at 12:58
  • \$\begingroup\$ Then you have to design the system to tolerate this stall in a sensible way and not leave incomplete blocks. Wait for 512 bytes, start writing it (accumulating more bytes in the meantime), then see if there's another block ready to be written. \$\endgroup\$ – pjc50 Jul 18 '16 at 13:02
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You'd want some sort of byte-orientated fifo, preferably in a block RAM in the FPGA. Then only start the transfer to EMMC once the fifo is part-full.

Even if I buffer a whole 512 bytes data array, I'll empty it faster than I fill it and it'll get slow again, eventually

Then you have to design the system to tolerate this stall in a sensible way and not leave incomplete blocks. Wait for 512 bytes, start writing it (accumulating more bytes in the meantime), then see if there's another block ready to be written

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