0
\$\begingroup\$

I am working on a board which is connected to a DC power source of 12V/20A. To control the power to the load , I am using a PMOS as high side switch as shown below :-

enter image description here

My Doubt is, from power dissipation point of view, I should worry about the source or drain of the mosfet?? or Its about the complete package that gets heated. Why I am asking is because I have a bigger pad pin for drain & a smaller one for drain. While routing, I need to provide vias & more copper. I want to understand whether if I only put more Vias @ source pad, can I get away with the heat or do I need vias for drain pad also. Layout is as below :-

enter image description here

If anyone has any suggestion regarding:-

  1. Power dissipation @ 12V/20A through IRF5305, please guide. Datasheet link :- http://www.infineon.com/dgdl/irf5305spbf.pdf?fileId=5546d462533600a4015355e378101995

  2. How to handle the dissipation?

\$\endgroup\$
  • \$\begingroup\$ I didn't read your whole question. But from the snapshot of the layout, it is very obvious that the chip is designed to dissipate the majority of heat through the large pad, which you have labelled as the drain. \$\endgroup\$ – mkeith Jul 16 '16 at 18:29
  • \$\begingroup\$ @ mkeith - So, is it only about the way it is designed or it depends on the way you use it. Please see the schematics & suggest. \$\endgroup\$ – Oshi Jul 16 '16 at 18:32
  • 2
    \$\begingroup\$ You should not be using an IRF5305 to switch 20A. Choose a FET with lower Rdson and then you won't have to worry about power dissipation! \$\endgroup\$ – Bruce Abbott Jul 16 '16 at 18:49
  • 3
    \$\begingroup\$ It does not depend on how you use it. The interface between the package and die is designed to transfer all heat efficiently to the large tab. The idea being that the large tab will transfer it to the PCB. \$\endgroup\$ – mkeith Jul 16 '16 at 19:03
2
\$\begingroup\$

You will want a similar number of vias on both source and drain pad. I would also recommend having a similar pad size. For the most part, all the current passing through one will pass through the other.

The best method would be to figure out what the maximum current this FET will provide. From here, you can consult the design rules or process design kit (PDK) to find what the resistance per via is for each layer. You would want to make sure you have enough vias (at each layer, and for all layers in series up to the final port) so that the combined resistance in parallel is low enough to only cause a negligible voltage drop.

A lot of the heat in planar technology, especially in this case, is caused by choking around vias. I would always err on the side of having too many rather than too few, unless you are severely area constrained. There are all sorts of failure mechanisms for vias under high current -- electromigration, 'peeling', etc.

I don't know what sorts of design software you have access to but there are quite a few vendors that can provide 'heat' maps for a given layout and set of stimulus. If you have this sort of tool you can simply add vias to the layers which are more red, iteratively, until the voltage drop to the top level is acceptable.

\$\endgroup\$
1
\$\begingroup\$

For a TO-262 the primary sink for the package is the tab. Optimizing heat flow coming from the tab is crucial in high-power applications.

\$\endgroup\$
  • \$\begingroup\$ I am not sure if I should know this already, but Can you please clarify, to which you are referring as TAB?? \$\endgroup\$ – Oshi Jul 16 '16 at 18:33
  • 2
    \$\begingroup\$ @Rishi: The large chunk of metal on the back of the package. \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 16 '16 at 18:38
  • \$\begingroup\$ @Rishi Also, see the data sheet. It says which connection is which. \$\endgroup\$ – winny Jul 17 '16 at 7:44

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.