So far in order to simulate CMOS circuits I relied on a library that I had to randomly download from Internet such as this one:


Inside the library the PMOS and NMOS model is defined using the BSIM3v3 model and I only have to create an instance of these transistors and wire them together and run the simulator.

My first question is that from where the professor of that class got this BSIM3v3 CMOS SPICE model?

Second question is: "Can I create my own transistors and extract such parameters and put them in my own library file?"

The only thing that comes to my mind is to use IC layout editors such as Cadence virtuoso or Microwind (I don't even know if they are the right software for this task, I just HEARD they can be used for IC design) to layout my transistor and then extract the SPICE parameter from them.

My ultimate goal is to design a simple standard CMOS digital cell library and use it for my more complex VLSI designs.

  • \$\begingroup\$ Hello, could you update the two links, one in the question and the other one in your answer ? Thanks! \$\endgroup\$
    – kellogs
    Commented Jul 26, 2023 at 16:32
  • \$\begingroup\$ @kellogs I updated the link: eda.ncsu.edu/ncsu-cdk \$\endgroup\$ Commented Jul 11 at 19:49
  • \$\begingroup\$ Unfortunately, the Colorado Analog IC design course is gone private. The models cannot be downloaded anymore. \$\endgroup\$ Commented Jul 11 at 20:34

2 Answers 2


Usually the transistor parameters are provided to the customer by the foundry after signing an NDA (non-disclosure agreement).

Transistor modeling and parameter extraction is a nontrivial task and usually based on a large number of measurements to get reliable data for the models. Of course with an automated setup this task can be done very efficiently. Just have a look at a BSIM model file and the number of parameters there to get an impression of the required effort.

Extraction of layout data does not result in transistors models. By extraction just the transistor geometry is obtained. Existing transistor models are needed for simulation.

I think the models you found on the internet are a good starting point as they seem to be based on an existing CMOS process.

  • \$\begingroup\$ Alright, at least it is good to know that such an NDA exists which makes my search online futile. I think I should sign on of those NDAs through my university and get my hands on some of these cute SPICE models. By reading your answer I conclude that using Microwind and Cadence is also useless to produce a transistor model. I let the thread to be open, maybe someone else come up with a better answer. Thanks. \$\endgroup\$ Commented Jul 18, 2016 at 16:55
  • \$\begingroup\$ What's wrong with the models you already have (5827_035.lib)? \$\endgroup\$
    – Mario
    Commented Jul 18, 2016 at 17:14
  • \$\begingroup\$ Nothing specifically wrong. I just didn't know the origin of it. I also can't verify if it really contains the parameters associated to the 350n technology. It seems to me so odd and bizarre that people can't freely get access to SPICE models of a fabrication factories. I expected i.e. MOSIS to provide all the SPICE models for all their supported technologies up in their website so people can easily download them and design and simulate their circuits and then submit the chip for fabrication. What makes them to hide their SPICE models? \$\endgroup\$ Commented Jul 18, 2016 at 17:22
  • 1
    \$\begingroup\$ I think the models are OK, they are very realistic if not even taken from a real foundry. It's common that you have to sign an NDA before you get any information. Not only for models but for any kind of information exchange. People want to protect their IP. \$\endgroup\$
    – Mario
    Commented Jul 18, 2016 at 17:46

I accepted Mario answer but later on I found a better answer by mysellf that would like to share here:

If you want to explore the IC design subject you can use the NCSU libraries provided at http://www.eda.ncsu.edu/wiki/NCSU_CDK for free.

Updated Link: https://eda.ncsu.edu/ncsu-cdk/

The library provided supports Cadence 5, and 6 (still in beta version), and provides insights and spice models down to 45nm technology.

For production IC design, you only have one option and that is to sign an NDA with the foundry and ask them to provide you with their factory specifications, which is a Design kit consist of: (1) Spice models (2) Technology files used in IC layout design (3) Datasheets, etc.


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