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PCIe gen 2 uses 8b/10b and the run length is 5. What is it for Gen 3? Thank you for help.

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closed as too broad by Bence Kaulics, Daniel Grillo, Sparky256, laptop2d, Dave Tweed Jul 23 '16 at 16:05

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  • \$\begingroup\$ 128/130b encoding. Don't know what the run length is. \$\endgroup\$ – Tom Carpenter Jul 18 '16 at 23:36
  • \$\begingroup\$ Yes! Thx. But what is the worst case run length? I suspect some sort of scrambling is also done on the data. \$\endgroup\$ – shparekh Jul 18 '16 at 23:43
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    \$\begingroup\$ Scrambling is done, yes, using the polynomial \$G(X) = X^{23} + X^{21} + X^{16} + X^8 + X^5 + X^2 + 1\$. If you can find a copy of the PCIe Base Spec Rev 3.0, the scrambler is described on page 213 onwards. \$\endgroup\$ – Tom Carpenter Jul 18 '16 at 23:47
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    \$\begingroup\$ This might also be useful reading. \$\endgroup\$ – Tom Carpenter Jul 18 '16 at 23:48
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PCIe gen 3 uses 128b/130b line coding, so absolute worst case run length would be 129 bits (128 scrambled bits + half of the 2 bit sync header). This assumes that the scrambling PRBS and transmit data exactly coincide and cancel to zeros for the entire 128 bit data block, which is possible but extremely unlikely. Note that in contrast with 64b/66b, the 128b/130b line code does not use a self-synchronizing scrambler. The DC wander is statistically bounded (as opposed to absolutely bounded) due to the scrambling.

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