PCIe gen 2 uses 8b/10b and the run length is 5. What is it for Gen 3? Thank you for help.
closed as too broad by Bence Kaulics, Daniel Grillo, Sparky256, laptop2d, Dave Tweed♦ Jul 23 '16 at 16:05
Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.
PCIe gen 3 uses 128b/130b line coding, so absolute worst case run length would be 129 bits (128 scrambled bits + half of the 2 bit sync header). This assumes that the scrambling PRBS and transmit data exactly coincide and cancel to zeros for the entire 128 bit data block, which is possible but extremely unlikely. Note that in contrast with 64b/66b, the 128b/130b line code does not use a self-synchronizing scrambler. The DC wander is statistically bounded (as opposed to absolutely bounded) due to the scrambling.