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Why is precharging so necessary while preforming read operation on SRAM/ DRAM cells?

For example in the SRAM 6T cell shown below,

enter image description here

Reading 0 requires bit line to discharge to 0; Reading 1 requires that bit line voltage is equivalent to logic '1' value.

Right?

So why can't this charge (in case of Q=1) occur via M4 and M6? i.e. why dont we consider M4-M6 as path strong enough to pull up the bit line?

Why do we rely on precharge value to give logic '1' on bit line?

Is it because NMOS M6 is a weak highpass?(due to the fact that NMOS is weak highpass)

Also, In case of precharging, is the precharge voltage = Vdd or Vdd/2 ?

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    \$\begingroup\$ DRAM and SRAM are not the same thing. Are you asking about both or just SRAM. \$\endgroup\$ – Tom Carpenter Jul 19 '16 at 18:49
  • \$\begingroup\$ Well both cases typically precharge high and use an NMOS to pull down. \$\endgroup\$ – jbord39 Jul 19 '16 at 19:32
  • \$\begingroup\$ @jbord39 DRAM is completely different - it uses a single transistor as a pass gate, and precharging is done to the mid supply to reduce the effect of charge sharing between the bit line and the bit capacitor. \$\endgroup\$ – Tom Carpenter Jul 19 '16 at 21:09
  • \$\begingroup\$ @Tom Carpenter "DRAM is completely different" no, if you read my comment they both typically precharge high and use an NMOS to pull down (obviously they 'are' different, or they would have the same name -- I related their characteristics in two ways, not every way). Yes, the WL during READ operation is precharged to vcc/2 but the internal storage bit is ideally rail to rail (although its voltage leaks when not refreshed). The write operation, however, is full rail. \$\endgroup\$ – jbord39 Jul 19 '16 at 22:16
  • \$\begingroup\$ Closely related: What is precharge in terms of Static Ram? \$\endgroup\$ – Dave Tweed Jul 20 '16 at 1:40
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The answers here are good regarding how in normal practice the bitlines will be charged to VDD/2. However that doesn't really answer the question, because it:

  • does not apply all the time (depends on the cache requirements and process technologies. I have seen plenty of caches that precharge to VDD because at low voltage operation VDD/2 can be too risky)

  • The 'canonical case' everyone learns first doesn't precharge to VDD/2, and this is the situation he is asking. There is still a good reason they go to VDD, though.

The main reason they charge the bitlines HIGH (in the circuit he is showing) and let them discharge is because the pass transistors are NMOS. This means they pass a very solid '0' but they pass a degraded '1'.

So rather than start the bitlines low and let them pull up through the NMOS (slower and weaker, can only pull to VSUPPLY-VTH), they will start the bitlines high and let them pull down through the NMOS (which can pull down more strongly, to a solid '0').

Another very good reason are the constraints on transistor sizing which must be met for proper writability/readability.

Read operation: M1 must be stronger than M5, so that the voltage divider formed between M5/M1 does not flip the bitnode.

Write operation: M2 must be weaker than M5, so that M5 can overcome the feedback loop when writing a '1'.

So, M1 > M5 > M2 (and M3 > M6 > M4). The PMOS are the weakest transistors in the whole cell, why use that to pull up?

On top of that, traditionally NMOS have been faster than PMOS. This is less true today in the lower process technologies (22nm, 14nm, 10nm, etc) but is still normally assumed.

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  • \$\begingroup\$ What is the need of having solid '0' when we're using sense amp? \$\endgroup\$ – Surfer on the fall Dec 2 '17 at 9:08
  • \$\begingroup\$ @Surferonthefall: Because you still need to be able to write the bit cells. On top of that, not all memory arrays use sense amps (they are not mentioned in this question). The sense amps would generally be used to "snap" the values of the complementary BL's faster than just the singular bitcell being read could provide. But during a write you still need to be able to fully pull down one or the other internal nodes depending on the write scheme, in the presence of noise and across low and high voltages. \$\endgroup\$ – jbord39 Dec 15 '17 at 23:20
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Precharging is not intended to deal with the ability to source drive current into a bit line. Precharge is intended to minimize propagation delay time.

If there is no precharge, the maximum voltage swing in a readout is from a "0) to "1" (or vice versa), which happens in T01.

Precharging ensures that the bit line is driven to voltage midway between "0" and "1", so that when the actual cell is read out, the line need only be driven from the midway voltage to either "0" or "1". This results in about one half the transition time (1/2*T01), and results in a faster memory.

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For DRAM, purpose of precharging is to close the current row and to allow activation of another row.

In the case when the same row cells are to be read, precharging can be done later when using Fast Page Mode DRAM.

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You can't drive a high-value through an NMOS switch. The output will stop rising fast once the output gets close to Vdd-Vt. Pre-charge allows the circuit to only have to drive a 0 value, which it can do well. I have attached a simple schematic to demonstrate the idea.

schematic

simulate this circuit – Schematic created using CircuitLab

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