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I'm writing a C program for ATmega64A which has a INT0 ISR. This ISR should be executed in case of INT0 falling edge OR if the TIMER3 goes overflow.

To avoid doubling the code I'd like to trigger Int0 ISR in the Timer 3 overflow ISR.

Unfortunately there is no such information in the datasheet. At least in the INTF register description section:

enter image description here

Does anyone tries this? Or maybe someone knows this in theory?

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  • \$\begingroup\$ Could you be doing more in that ISR than you ideally should? \$\endgroup\$ – JimmyB Jul 20 '16 at 17:41
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Nope.

Writing a 1 to the flag will clear it. Writing a 0 will do nothing.


However, if you are using avr-libc and want to have two (or more) vectors having exactly the same code, this is possible. You use interrupt aliasing. An example (from here):

ISR(PCINT0_vect){  
    ...  
    // Code to handle the event.
}

ISR(PCINT1_vect, ISR_ALIASOF(PCINT0_vect));

In this example both PCINT0 and PCINT1 will share the same interrupt code - both entries in the vector table will point at the same function. This may be sufficient for your needs.

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  • \$\begingroup\$ So is there any solution for such task (run one code from several ISR's)? \$\endgroup\$ – Roman Matveev Jul 20 '16 at 12:36
  • \$\begingroup\$ @RomanMatveev see my edit - I had to go look up the syntax. \$\endgroup\$ – Tom Carpenter Jul 20 '16 at 12:39
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    \$\begingroup\$ ... or you could just create each ISR as a shell (wrapper) that calls a common sub-function. \$\endgroup\$ – Dave Tweed Jul 20 '16 at 12:43
  • \$\begingroup\$ @DaveTweed that can be done, but calling functions from ISRs is not always a good idea at least with avr-libc/avr-gcc. It can result in extra overhead from additional registers being pushed and popped, and also adds overhead from the call/ret instructions. Aliasing if available is a nice clean method which results in zero overhead on top of the original interrupt routine. \$\endgroup\$ – Tom Carpenter Jul 20 '16 at 12:46
  • \$\begingroup\$ Aliasing has it's own disadvantage: ISR's should be EXACTLY the same. So I can't do INT0 ISR and timer register clear from Timer ISR in the same time. \$\endgroup\$ – Roman Matveev Jul 20 '16 at 12:54

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