Oscillation in Voltage Rectifier / Scaling Circuit

Question

I am working on creating a circuit that will scale +/- 12v input to a unipolar 3.3v centered around 1.65v, in order to scale the kind of CV used in modular synthesis systems to work with the ADCs on the STM32F4 microcontroller, which want to see a 0-3.3v input.

I am encountering problems with noise, specifically a strange oscillation around 8.6 MHz. I have tried adding filtering capacitors, which helps somewhat, but does not completely eliminate the problem, so I think there is something wrong with my circuit.

To accomplish the scaling of voltage I put the input through a 16k/100k voltage divider to scale the input to +/- 1.65v, which is sent into a buffer. I then add a 1.65v bias and send it through two unity gain inverting amplifiers. I get the 1.65v bias by dividing the power supply and sending it through a buffer in the same manner that I do the input. I am using the LM324 quad op-amp, which I power off a +/- 12v supply.

Is there anything flawed in my methodology here that could be causing this unwanted noise, or a better/cleaner way I could be doing this?

Here is the schematic:

P.S. disregard where it says LT103 on the schematic, I am using the LM324, a quad op-amp

Answer 1

^{simulate this circuit – Schematic created using CircuitLab}

You don't need any op amps, at all - maybe a single buffer.

Answer 2

You are making this way too complicated. For reference, here is your circuit:

There are a number of ways to simplify this. The two back to back inverting buffers are just silly. Why not the obvious single non-inverting buffer? Also, the first inverting buffer isn't actually unity gain. Note that the signal coming in has the impedance of R4//R6, which is 5 kΩ. With the feedback resistor being 10 kΩ, the U2 stage will have a gain of -2.

All you really need is this:

R1 and R2 form a voltage divider that reduces the gain of the input signal. Without V1, that would be just scaled about ground. V1 adds a offset. By separating the desired gain and desired offset, we can compute the values easily.

We actually have three degrees of freedom and so far only stated two constraints. The remaining constraint can be expressed as the input or output impedance of the divider. For now, we'll just arbitrarily pick 10 kΩ for R1 to nail down the third degree of freedom. Later you can scale all resistors by the same amount to adjust the impedances.

The input signal has a range of 24 V and the output has a range of 3.3 V. Therefore from the gain alone we know that the R1,R2 voltage divider must have a gain of (3.3 V)/(24 V) = 0.138. With R1 = 10 kΩ, R2 must be 1.59 kΩ.

Now we only have a single constraint left and a single value to find, which is the voltage of V1. One way to solve this is to pick any one operating point and find what V1 must be. I'll pick 0 V in, which we know must result in (3.3 V)/2 = 1.65 V. So now we have a voltage divider with the top being at 0 V, the resistors being 10 kΩ and 1.59 kΩ, the output being 1.65 V, and we need to find the bottom voltage. From basic voltage divider math, V1 is 1.91 V.

So we now have:

At this point it is a good idea to do a check to make sure we didn't mess up anything. You could, for example, put 12 V in and verify that you get 3.3 V out. I've done that and it checks, but I'll leave this is a exercise for you to do on your own.

This circuit will work nicely, but requiring a 1.91 V source is a bit inconvenient. Note that from the rest of the circuit's point of view V1 and R2 form a Thevenin source with a voltage of 1.91 V and a impedance of 1.59 kΩ. We can create exactly the same Thevenin source from your existing 12 V supply:

We have two constraints. The R3,R4 voltage divider by itself must produce 1.91 V:

  (12 V) R4 / (R3 + R4) = 1.91 V

And the parallel combination of R3 and R4 must be 1.59 kΩ:

  (R3 * R4)/(R3 + R4) = 1.59 kΩ

I'll skip the 8th grade arithmetic, but that comes out to R3 = 10.0 kΩ and R4 = 1.90 kΩ. So here is the final circuit:

Yes, it really is that easy.

Note that the input impedance is R1 + R3//R4 = 11.6 kΩ, and the output impedance is R1//R3//R4 = 1.38 kΩ. If those are acceptable, then you need to do nothing more. All the resistors can be scaled by the same amount to change these impedances.

If the input impedance is still too low at the maximum signal impedance your A/D needs, then you can use a single unity gain buffer following this resistor network. In that case, scale the resistors to get the desired input impedance. The output impedance will be that of the unity gain buffer, and independent of the resistors.

So at most, your circuit looks like the three resistors above followed by a unity gain buffer.

Again, yes it really is this simple.

Answer 3

^{simulate this circuit – Schematic created using CircuitLab}

The above circuit could work for you if the input is a digital signal. The first stage converts the +12/-12V into +3.3V/0V. The second stage removes high frequency noise, set using R3/C1.

More details would be nice, to help determine the constraints.

• For example, is the input signal digital in nature? If so we can use a simpler comparator instead of linear amplifier.

• Do you care about the linearity of the output? If not, even if the input is a sine wave, we could drive the outputs rail to rail to achieve 0-3.3V.

• What is the frequency range of the inputs? Does this operate at DC voltage? Does this operate at 40kHz?

Depending on your needs this circuit could work (below is a linear-type amplifier):

The first stage scales the 24V differential input voltage into a 3.3V differential voltage biased around Vb. The RC network forms a low-pass filter to help with the high frequency noise you mentioned.

The second stage is just an buffer to provide some drive current. You can replace this with inverting op-amp if you need to correct the polarity.

In practice I would probably generate the reference voltage using a trim-pot, since due to non-zero input offset voltages you may need to tweak it a little for a closer voltage range.