I understand that it is best practice to register the outputs of all modules; so, I want to do that. However, I'm unsure what exactly it means to register an output signal.

I.e. Do I have to include the signal in a clocked process to ensure that it is registered? Or can I just use a concurrent statement?

It could be one of two ways:

entity mgmt_regs is
  port map
    -- Internal host bus interface
    clk             : in std_logic,
    in_signal       : in std_logic,
    out_signal      : out std_logic
end mgmt_regs;

architecture RTL of mgmt_regs is
signal sIn_signal    : std_logic;
signal sOut_signal   : std_logic;


sIn_signal <= in_signal;

-------------------- THIS ONE?? -------------
out_signal <= sOut_signal;-------------------

   if (rising_edge(clk)) then
       --do other stuff

       ------------------------- OR THIS ONE?? -----------
       out_signal <= sOut_signal; ------------------------
   end if;
end process;

end architecture RTL;

Also, I was wondering about cases when I have a top entity. If my subcomponents have their signals which are going to connect to the output part of my top entity and inside those lower entities their signal is registered, do I still have to register the output signal in the top sheet or can I just connect it to the output port?


In general (99% of the time) you will need a clock signal for each register.

But, verilog/VHDL you do not have to specify the exact register implementation.
You just tell it, this is a bitnode which is either level triggered or rising edge controlled by some signals.

For example if you are using a less common design style, like MS-CMOS, you may not need a clock for each register. In this case, the register could be represented using an SR latch, which does not need a clock. But even in this case it would be common to 'staticize' the SR latch's output using a regular type flip flop (which requires a clock). There are other examples but they would vary a lot.

Each time you add a register into a serial path, you create a cycle boundary (a lock and dam type system controlled by the clock). So in regards to your last question, it depends on the desired functionality. But I think your case no, you do not need to register the outputs. If the inputs are all coming from registers, the output will be 'in that cycle'. If you add a register at the output it will push that output into the next cycle.


The term 'register' refers to a logic memory element, which is nearly always a flip-flop. Most of the time in designs, you'll find it will be a D-type Flip-Flop or DFF.

The idea of all module outputs being from registers is sometimes put across as a rule of thumb to be aimed for. However, it's very subjective.

It's a good idea if, for example, you have lots of modules being re-used in different designs for FPGAs/ASICs with plenty of registers.

It's a bad idea if you can't afford, or don't want to waste time on, the latency caused by the extra clocks for the signals to reach destinations. Or if you're using a small gate device or if your target device will be very full anyway.

(I'm sure there's more reasons people can give but you get the drift. I favour the 'no' camp but my circumstances are usually those I've listed for 'bad idea'. My designs are often produced by me alone from scratch.)


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