I understand that it is best practice to register the outputs of all modules; so, I want to do that. However, I'm unsure what exactly it means to register an output signal.
I.e. Do I have to include the signal in a clocked process to ensure that it is registered? Or can I just use a concurrent statement?
It could be one of two ways:
entity mgmt_regs is
port map
(
-- Internal host bus interface
clk : in std_logic,
in_signal : in std_logic,
out_signal : out std_logic
);
end mgmt_regs;
architecture RTL of mgmt_regs is
signal sIn_signal : std_logic;
signal sOut_signal : std_logic;
begin
sIn_signal <= in_signal;
-------------------- THIS ONE?? -------------
out_signal <= sOut_signal;-------------------
process(clk)
begin
if (rising_edge(clk)) then
--do other stuff
------------------------- OR THIS ONE?? -----------
out_signal <= sOut_signal; ------------------------
end if;
end process;
end architecture RTL;
Also, I was wondering about cases when I have a top entity. If my subcomponents have their signals which are going to connect to the output part of my top entity and inside those lower entities their signal is registered, do I still have to register the output signal in the top sheet or can I just connect it to the output port?