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I've used the footprint wizard to generate QFN package, the result:enter image description here

My question is, if it's OK to remove the vias since I want to put some components to save same room?

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    \$\begingroup\$ Which IC will you use? \$\endgroup\$ – pipe Jul 24 '16 at 10:44
  • \$\begingroup\$ well not only one for example : CAP1214 & SAML21E \$\endgroup\$ – Engine Jul 24 '16 at 10:45
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    \$\begingroup\$ You need to show us 'before' and 'after' layouts as we have nothing to look at in terms of the changes that would occur. \$\endgroup\$ – Sparky256 Jul 25 '16 at 3:53
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These vias serve two purposes:

  1. the center pad of a QFN package is often a ground pin. And ground pins must usually be connected to a ground plane or similar using a low-inductance path. Since every wire has inductance, and vias have a lot of inductance, having as many parallel vias between that pad and a ground plane is highly desirable. However, if your component doesn't do anything with large fast-switching currents or at high speeds, you might get around having that many pins
  2. that pad is commonly called "thermal pad" – for a reason. The vias' job is to get the heat out of the device into copper layers as efficiently as possible. Whether, and how many of these, you need depends completely on your IC and the operational conditions. You will need to estimate the power converted to heat, the difference to environmental temperature, and based on that, the heat transfer capabilities necessary, before you can apply rules of thumb or proper simulations to see with how little vias you can get away with.

In essence, if you're on a four (or more) layer board, and your IC doesn't seem to output a lot of heat, you'll probably be fine just putting vias from top layer to ground layer there, and not the whole way through (if your production technology allows for non-continuous vias).

If you're on a two-layer board, or need to get significant heat out of the chip: ditch the idea of removing these vias.

Completely getting rid of these vias will only be possible if you don't need the pad to attach to ground – which is an unlikely case, but I'm sure it's OK for some components. Things that deal with high frequencies (for example, touch sensors), or things that run at high processor clocks (for example, ARM CPUs), or things that require high-quality analog signaling (for example, ADCs) are surely not among the things I'd remove the ground vias from.

Also, almost all datasheet for QFN chips will come either with some section on recommended layout, or you'll find some application note explaining the same – refer to your IC's manufacturer's documentation on what you should do.

Another note: You seem to be designing a crazily high-density device if you're worried about the 4x4mm of a 0.5mm pitched QFN-16's reverse side... Maybe you should re-evaluate your component choices. There's microcontrollers that integrate the touch sensor, so you save that amount of space.

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    \$\begingroup\$ Exactly why I asked about the chip - The vias are probably unnecessary for CAP1214 (1 mA), but necessary or at least advisable for SAML21E. \$\endgroup\$ – pipe Jul 24 '16 at 10:50

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