# Is this address decoding circuit correct?

The problem is to design an address decoding circuit for two 4Kx8 RAM chips at the 2050H . We have 16 address lines. So, for 4Kx8 RAM we need 12 address lines to address the memory. Remaining can be used for deriving CS' (chip select) signal.

Here, For RAM 1 we have

For RAM 2 we have

Bold = A12

So, if we use a 1x2 decoder as in the picture, and A12 is the input. The chips will be selected depending on the state of A12. It will work fine until ending address is used. What happens when someone tries to access the ending address?

Your circuit will not work as intended. This is not a simple, or typical, memory decoding problem since the starting and ending addresses are not integral multiples of the RAM capacities - 4K (4,096 decimal) or 1000 Hex.

You must account for the 50 hex offset in the supplied addresses so that the bottom supplied address (2050h or 3050h) aligns with address 0000 in the RAM(s). This will require some sort of adder logic.

If the RAMs were larger capacity, you could likely get away with this type of simple decoding because the required space of X050 to Y04F would all fit within the larger RAM space. Must there be two separate RAMs in the solution? Must the write and read action of the RAMs be strictly combined to the 2050h to 404Fh area of the RAM? In other words are there other devices in the adjacent memory space (e.g. at 204Fh and 4050h) that would collide with RAM operations made beyond the specified source address space? These are all considerations that would perhaps make the design of the decoder.

• Hi, This was a question given to us by our TA. I think this was intentional and they want us to solve this offset problem. They haven't talked about this in class and I think they have left it up to us to research and come up with an answer. How do i fix this? Where can find necessary materials on this topic? Jul 24 '16 at 15:29
• @Happyfeet: Use your powers of creative thinking! I would start by looking at binary adders/subtractors. Figure out how to add the -50h offset to the source address, in addition to the obvious decoding, so that the 2050h source address combination ends up accessing slot address 0000 of the 4K RAM. Jul 24 '16 at 20:10

According to the schematic the listed starting and ending addresses are not correct. In fact the last address of the 4 listed is not mapped to either of the memory chips.

According to the schematic, one of the starting address might be 2000H and the ending might be 2FFFH. And the starting address of the other chip might be 3000H and the ending might be 3FFFF. The answer has to be somewhat ambiguous as there are no chip part numbers.