Using a snapshot of an eval board design below as an example, voids are added to the ground plane on layer 2 (green) right underneath the analog signal path on layer 1 (yellow). This causes the analog traces to reference the ground plane on layer 3 instead. I understand that this increases trace width, hence improved impedance matching and decreased signal loss at the trace-to-pad junctions.
What is the best way to determine the minimum width of the voids that guarantees that the signals do not reference layer 2? I assume this is based on the trace widths and the layer separations.