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In the circuit below, what sets the voltage at the source of the NMOS if the current source is set to 0A?

schematic

simulate this circuit – Schematic created using CircuitLab

If I run the circuit through ngspice and do a DC sweep of the current source value, I get a defined voltage at X for 0 current.

This is as far as my reasoning gets:

  1. The current source is drawing no current.
  2. The backgate is grounded so there's enough of a voltage to form a channel, even though the source is floating.
  3. There's no current drawn through the channel as there's nowhere for it to go, so it can't cause a voltage drop.

Misc notes:

  • The current source looks like an infinite resistance in the small-signal model, effectively floating the source connection.
  • NMOS is diode-connected, so should be in the active region if \$V_{gs}\$ exceeds the threshold voltage.
  • I don't have a discrete NMOS with a backgate connection to try it on the bench.

I suspect the backgate or maybe some other leakage current.

Is this voltage real, or is it some artifact of the modelling?

[* Razavi, 1st edition(?), example 2.8]

Update

I ran a transient analysis as suggested below, but \$V_{X}\$ still remains below \$V_{DD}\$ near time zero. I'm strongly suspecting leakage currents now...

Plot of Vdd and Vx

I've also plotted the backgate current: ~9pA around time zero (not shown). This seems like a puny current to produce that voltage drop.

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    \$\begingroup\$ ... Leakage through the body diode. \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 26 '16 at 18:38
  • \$\begingroup\$ voltage between: Vcc & X: 0V, Vcc & GND: Vcc, X & GND: 0V \$\endgroup\$ – user86234 Jul 26 '16 at 18:50
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    \$\begingroup\$ Hint: In your simulation put a delay from time 0 till you start the linear ramp of current in the current sync. You should notice that during the delay period the source voltage will be right at the Vdd level since no current is flowing. At the moment the current rises up to just a smidgen the voltage at source becomes less than Vdd due to the VGSth value if the FET to allow the channel to open. \$\endgroup\$ – Michael Karas Jul 26 '16 at 18:57
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As per my comment above here is a simulation result from LTSpice using a 2N7002 model.

enter image description here

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Simulations can have multiple valid results, some simulators try to discard results that are trivial or unlikely. These often includes solutions where all currents are zero.

In this case the current source is ideal and imposes the condition that the current into the drain (?) of the transistor is zero. This will be the case for any voltage at node X that equals the voltage Vdd.

It would be interesting to see if Vdd actually equals the voltage at node X.

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voltage between: Vcc & X: 0V, Vcc & GND: Vcc, X & GND: 0V

That's obviously contradictory, so you've broken the simulator. It's probably trying to divide by zero somewhere and refusing.

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I would expect the voltage at that node to be created by a capacitance when the NMOS is fully off. If nothing else, this cap would be made up of the source capacitance of the NMOS (and in real situations the output capacitance of the current source, along with all parasitics along the way).

As time increases from when this voltage is set, leakage through the NMOS will charge or discharge the node cap slowly.

$$ V = \frac{Q}{C} $$

So even though 0A flows in the current source, some can flow from the supply to charge up the nodal cap.

CMOS gates in general draw no static power (except leakage which is very low). So, similar to this situation, their voltage is created in lieu of a static current source. Again, this is just charge stored on the gate capacitances of the subsequent FET's (along with parasitics of FET's, wires, etc).

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