# Possiblity of Using Transistor as Resistor

I would like to know it if is posible to use NMOS transistor to act as a resistor with a sinusoidal power supply ?

The circuit I have is very simple; it consists of a 20Vpp-sinusoidal source connected to a resistor (100 M to 700 M Ohm) then to ground. However, I want to replace the resistor with an NMOS transistor such that the circuit behaves in a similar manner.

So, would it be possible to do that without a DC source? Given that I can design my own NMOS transistor with any parameters values I need, such as Vth, mobility, W/L,...etc

I know for a fact that if the transistor is to act as a resistor it must be in the triode region where VGS > Vth & VDS < VGS - Vth, but I am not sure if it is going to work with no DC biasing source.

• To keep it in the triode region at the exact point where the Rds is the value you want, you need some feedback. The easiest is to use an opamp to drive the fet gate, then. But your requirement is strange. You should provide more information about the ultimate goal you're trying to achieve.
– dim
Jul 27 '16 at 7:51
• But... why? Are you trying to make a resistor switchable? A resistor that can change its value? You can't just decide to replace a resistor by a mosfet without a real goal behind, can you? Tell us more about that, because we won't be able to make relevant, good-quality answers otherwise.
– dim
Jul 27 '16 at 8:03
• Linear regulators typically use a transistor as a (variable) resistor; see, for example, Understanding LDO Regulators (PDF). But what problem are you trying to solve?
– CL.
Jul 27 '16 at 8:08
• Sounds like you're actually designing an IC. If that's true, you must inform us about this quite vital information.
– pipe
Jul 27 '16 at 10:24
• I do not want to use resistors because they are too bulky for my application. And yes, I am designing an IC circuit for a research purpose, and I've reached to that situation where I have only AC feeding transistors which are meant to be resistors. Jul 27 '16 at 10:44

This technique of using FET's as resistors is commonly done in ICs because the resistors have to be huge to get any substantial resistance values. Keep in mind that the simulations I have below are ideal. In an IC, especially smaller technologies, you will have significant channel length modulation. This means that in saturation and increase in Vds increases the current. This would actually soften the quadratic behavior of the square law-connected NMOS in your schematic.

However, it works best if you can bias the FET's with DC values. I would also like to point out that the FET's in IC are way different than the IRF530's which another user simulated. Those are power FET's and completely different beasts from the FET's on an IC.

I have attached a simulation showing the setup you have now. The FET's are just ideal models, you would need to include the actual models into your sim. I plotted V-I (straight line implies linear resistance) on the right side, you can see it's not perfectly linear. This is because hooked up like that the FET acts as a square law device. VGS = VDS, the FET is in saturation, and:

$$I_d = A*(V_{gs}-V_t)^2$$

If you take the differential resistance as dV/dI:

$$dI/dV = R_d = \frac{1}{2A(V_{gs}-V_t)}$$

So, quite non-linear.

If instead you bias with a constant VGS, you can keep the FET in the "ohmic" or linear region. I didn't spend much time but you can see the idea from the simulations below.

If you bias with a DC source it looks a lot better. You will need to get the actual FET models for the fab you are using, and include them in your simulations. Check the V-I over your operating range and attempt to make it as linear as possible.

If you can, combine a PMOS / NMOS w/ DC bias for a much more linear V-I curve, which means a near-constant R value. Since you are designing an IC you have control over the relative sizing of the NMOS/PMOS; play with this knob to help compensate better:

As I was thinking about it, if you can use a diode there is no reason you can't just produce a DC-ish voltage to bias the FET. For the cap, use another MOSFET gate with it's source/drain tied to ground (sometimes also ties S/D/G, the ground connection is through the substrate) check your design rules for which is preferred in your technology).

So finally below, is a very linear resistor biased with a generated DC voltage.

Just for reference, this is what the VI curve looks like for the circuit the OP posted. Each device is acting as a square law device and the whole thing doesn't start conducting until 3*VGS + Vdiode, which is very exaggerated in a power FET, since their threshold voltages are ~7 times that of IC FET's.

That won't work because if you apply an AC sinusoid to the gate, and the transistor isn't biased in some way, then when the AC signal goes more negative than Vth, the transistor will be cut off and will remain cut off for the entire negative half-cycle, so the resistance of the transistor will only change when the gate is more positive than Vth.

EDIT:

It appears that there's more to this than meets the eye.

Take a look at the red trace, below, and then run the attached LTspice circuit list to zoom in around zero G$\Omega$.

Version 4
SHEET 1 880 680
WIRE 192 0 112 0
WIRE 336 0 256 0
WIRE 416 0 336 0
WIRE 416 48 416 0
WIRE 336 128 336 0
WIRE 368 128 336 128
WIRE 416 176 416 144
WIRE 416 176 336 176
WIRE 416 208 416 176
WIRE 336 288 336 176
WIRE 368 288 336 288
WIRE 416 336 416 304
WIRE 416 336 336 336
WIRE 416 368 416 336
WIRE 112 384 112 0
WIRE 336 448 336 336
WIRE 368 448 336 448
WIRE 112 512 112 464
WIRE 416 512 416 464
WIRE 416 512 112 512
WIRE 112 592 112 512
FLAG 112 592 0
SYMBOL nmos 368 208 R0
SYMATTR InstName M1
SYMATTR Value IRF530
SYMBOL nmos 368 48 R0
SYMATTR InstName M2
SYMATTR Value IRF530
SYMBOL nmos 368 368 R0
SYMATTR InstName M3
SYMATTR Value IRF530
SYMBOL diode 192 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL voltage 112 368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 20 1000)
TEXT 128 544 Left 2 !.tran 5m uic

• I am actually applying the AC to the drain of the transistor which is also connected to gate. So I have VDS= VGS and the only way to make that transistor operates in triode region is to make Vth below 0, which I achieved already. But the question is, is it possible to do such a thing ? Do I need a DC supply to force the transistor act as a resistor in triode region ? Jul 27 '16 at 10:47
• Moreover, I can eliminate the negative cycle of the sinusoidal by adding a diode at the source. Just to make sure VGS does not go below Vth. So that's not a problem here. Jul 27 '16 at 10:49
• @Fahad: I apologize for not having brought this up earlier, but you could allay a great deal of confusion (for me, at least) if you'd edit your question by adding a schematic describing what you have in mind. As it stands now, you seem to be saying that you want the transistor's drain-to-source resistance to change only on the positive half-cycles of the input signal's excursion, while earlier it seemed you wanted the $R_{DS}$ to change over the entire cycle. Can you clear up what it is you want to do, please? Jul 27 '16 at 18:49
• I have attached the schematic of the circuit I am talking about. Jul 28 '16 at 6:09
• Can anyone expect the behavior of this circuit ? Will there be a current flowing through the transistors ? Giving that the amplitude of the sine wave is 15 V and all the transistors are identical and have Vth = -1 V Jul 28 '16 at 6:10