I'm looking to create a schematic block from a vhdl file in Altera'a Quartus software.

I've been using File->Create/Update->Create Symbol Files for Current file

The file compiles okay and I get the following message:

enter image description here

with the following warnings:

Warning (10445): VHDL Subtype or Type Declaration warning at fixed_pkg_c.vhdl(1470): subtype or type has null range
Warning (10445): VHDL Subtype or Type Declaration warning at fixed_pkg_c.vhdl(1471): subtype or type has null range
Warning (10445): VHDL Subtype or Type Declaration warning at fixed_pkg_c.vhdl(1472): subtype or type has null range

What I'm expecting to find is a .bsf file in the project directory that I can then use to create a schematic block.... but it doesn't appear (I've searched entire hard drive).

1. Am I correct to expect that a .bsf file has been created?

2. What debugging/troubleshooting steps should I take?

Quartus II 64-bit v13.0.0


here's the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library floatfixlib;
use floatfixlib.fixed_pkg.all;

entity gate_zero_initiato is 

        power_on      : in std_logic;   
        E1_A      : out std_logic;
        E2_A      : out std_logic;
        E3_A      : out std_logic;
        E4_A      : out std_logic;
        E5_A      : out std_logic;
        E6_A      : out std_logic;
        E7_A      : out std_logic;
        E8_A      : out std_logic


end gate_zero_initiato;

architecture behavior of gate_zero_initiato is



        if (power_on'event) then

                E1_A <= '0';
                E2_A <= '0';
                E3_A <= '0';
                E4_A <= '0';
                E5_A <= '0';
                E6_A <= '0';
                E7_A <= '0';
                E8_A <= '0';

            end if;
    end process powerup;

end behavior;
  • \$\begingroup\$ Can you post your VHDL code? Did you try in another Quartus version? \$\endgroup\$ Jul 27 '16 at 15:18
  • \$\begingroup\$ @ClaudioAviChami Code added. No I haven't... \$\endgroup\$
    – atomh33ls
    Jul 27 '16 at 15:28

The problem with your code is that, as it is written, it is not synthesizable. Try to synthesize it and check for yourself. Write code able for synthesis and the problem will disapear.

One way to make your code able for synthesis is by using this if condition:

    if (power_on = '1') then
  • \$\begingroup\$ Thanks, a .bsf file is still not created after amending the code. Does your answer mean that quartus will not create .bsf files if the vhdl code is not synthesizable? How does one debug/check for synthesizability? \$\endgroup\$
    – atomh33ls
    Jul 28 '16 at 8:18
  • \$\begingroup\$ I guess that was the reason, for when I corrected the errors in your code, Quartus produced a symbol for me (I use version 15.1). To check your code make a project with your code and run Analysis and Elaboration \$\endgroup\$ Jul 28 '16 at 17:12

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