Yes, it is possible. You must ensure, however, that all accesses to the resources that will be used by both cores are appropriately synchronized.
You'll certainly want to assign some RAM areas for exclusive use by the bare-metal firmware core. These areas won't need synchronized access since you can guarantee FreeRTOS cannot access it. But to guarantee this, you must configure FreeRTOS so it doesn't ever use this part of the memory.
On the opposite, you must ensure from your bare-metal firmware that you don't screw up with the memory zones known and managed by FreeRTOS.
If you need interaction between both cores (and you'd certainly have to), you need some special areas that are shared between both systems. These areas will need specific precautions when being accessed. You'll need mutexes that work on multi-cores (using LDREX/STREX), and you'll need them to be consistently implemented on both sides.
There may also be specific precautions to take for the shared memory, to ensure the local caches of both cores are consistently invalidated when there is an update. Or, to simplify things, you may actually want to disable the whole caching for these specific areas (configure them as if they were memory-mapped peripheral zones).
You could eventually share some peripherals among cores and use mutexes to synchronize accesses, as you do for memory. But I'd avoid doing this. I'd designate a responsible core for each peripheral, and, if there are cases where the other core needs to access it, use some shared memory to pass data and trigger events. This way, you ensure that the whole communication with a given peripheral can be prioritized appropriately from a single core.
All in all
This is not easy. Obviously, you need to make a customized version of FreeRTOS to handle the specific memory segmentation and sharing. And you need to develop advanced synchronized access from your bare-metal firmware. This is certainly much more difficult than using, on both sides, an existing RT operating system that is already able to work on multi-core processors.