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Is that possible to run bare-metal software in CPU0 and FreeRTOS in CPU1 since the ARM Cortex A9 is a dual core processor. I am asking this out of curiosity. If anyone has accomplished this before, do you mind sharing how you did that?

I am using Zedboard FPGA with ARM Cortex A9 PS.

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  • \$\begingroup\$ Interesting question. I doubt you can assume the two cores independent enough to not effect each other with out supporting software. I'm thinking the answer is to run virtual box or some other software that you would normally install two independent operating systems on top of. In your case, none & FreeRTOS. \$\endgroup\$ – st2000 Jul 27 '16 at 12:20
  • \$\begingroup\$ This is called asymmetric multiprocessing. Although I never did myself, Xilinx has a couple application notes on the subject. You may have problems with shared resources like cache, and thus might be better off having FreeRTOS on cpu0 and bare-metal on cpu1. Anyways, it is definitely possible to do so, just be careful about it. \$\endgroup\$ – Jonathan Drolet Jul 27 '16 at 12:24
  • \$\begingroup\$ Thank you st2000 and Jonathan Drolet. I will try it out and keep this posting. Can I have the exact name of the documentation that I can look at? Thank you! \$\endgroup\$ – user9870 Jul 27 '16 at 12:26
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    \$\begingroup\$ @Kin There is xapp1078 (running Linux+bare) and xapp1079 (running two bare). I never used FreeRTOS, but from what I understand it is much closer to baremetal than linux, do you may be better off with xapp1079. It will be easier to start from the example and upgrading the application than start from scatch! \$\endgroup\$ – Jonathan Drolet Jul 27 '16 at 19:59
  • \$\begingroup\$ @jonathan this is indeed helpful!thank you very much I will have a look on it. \$\endgroup\$ – user9870 Jul 27 '16 at 20:01
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Yes, it is possible. You must ensure, however, that all accesses to the resources that will be used by both cores are appropriately synchronized.

This means:

Regarding memory

You'll certainly want to assign some RAM areas for exclusive use by the bare-metal firmware core. These areas won't need synchronized access since you can guarantee FreeRTOS cannot access it. But to guarantee this, you must configure FreeRTOS so it doesn't ever use this part of the memory.

On the opposite, you must ensure from your bare-metal firmware that you don't screw up with the memory zones known and managed by FreeRTOS.

If you need interaction between both cores (and you'd certainly have to), you need some special areas that are shared between both systems. These areas will need specific precautions when being accessed. You'll need mutexes that work on multi-cores (using LDREX/STREX), and you'll need them to be consistently implemented on both sides.

There may also be specific precautions to take for the shared memory, to ensure the local caches of both cores are consistently invalidated when there is an update. Or, to simplify things, you may actually want to disable the whole caching for these specific areas (configure them as if they were memory-mapped peripheral zones).

Regarding peripherals

You could eventually share some peripherals among cores and use mutexes to synchronize accesses, as you do for memory. But I'd avoid doing this. I'd designate a responsible core for each peripheral, and, if there are cases where the other core needs to access it, use some shared memory to pass data and trigger events. This way, you ensure that the whole communication with a given peripheral can be prioritized appropriately from a single core.

All in all

This is not easy. Obviously, you need to make a customized version of FreeRTOS to handle the specific memory segmentation and sharing. And you need to develop advanced synchronized access from your bare-metal firmware. This is certainly much more difficult than using, on both sides, an existing RT operating system that is already able to work on multi-core processors.

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