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Disclaimer: I am not sure if this is the right place to ask this.

I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron MT46H32M16LF or the Winbond W949D6CBHX6E, which operates the same way). The clock is transmitted using the differential pair ck, ck_n. In the constraints file for my design, the signals are defined as DIFF_MOBILE_DDR (while most other signals are defined as MOBILE_DDR: they don't seem to cause troubles).

My first try was to set ck to the clock, and ck_n to not(clock). However, I get the following error message in Xilinx ISE:

The I/O component "ck" has an illegal IOSTANDARD value. The IOB component is configured to use single-ended signaling and can not use differential IOSTANDARD value DIFF_MOBILE_DDR. Two ways to rectify this issue are: 1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O connectivity by instantiating a differential I/O buffer.

(and a similar message for ck_n)

My guess is that I have to use a differential I/O buffer. How can I do this is Xilinx ISE?

Googling didn't lead to much. A related question which seems to suggest that there is some HDL from a library that does what I want, but I still have no idea which one.

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    \$\begingroup\$ There are many different type of differential I/Os, the type you have here is usually pretty easy to connect to. If you want to connect to a LPDDR memory, you can use the MIG to create a memory controller for you and it will create all the necessary files and constraint files for you, including the pin-mapping for the IOs. \$\endgroup\$ – FarhadA Jul 28 '16 at 9:00
  • \$\begingroup\$ The interface looks very complex though, and the user guide for mig is nearly 600 pages... \$\endgroup\$ – Ruben Jul 28 '16 at 11:50
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    \$\begingroup\$ Writing a DDR memory controller is very hard work. Maybe our DDR controller for Spartan-3/Cyclone III can help you with some issues, which you will face... The controller is split into a generic and an FPGA (physical layer) dependent part. You could adapt our Spartan-3 phy layer for the Spartan-6 and provide your solution as an contribution to our library :). You can find our usage and test example(s) here. \$\endgroup\$ – Paebbels Jul 28 '16 at 23:24
  • \$\begingroup\$ Why would anyone want to make their own DDR controller when you can use the ones already available by the MIG? I am sure this memory is supported so you just need to run the MIG interface and connect it to the right pins on your FPGA and you will be good to go! \$\endgroup\$ – FarhadA Jul 29 '16 at 12:27
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    \$\begingroup\$ @FarhadA Educational and recreational purposes. \$\endgroup\$ – Ruben Jul 29 '16 at 15:58
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I found my answer on page 260/261 of this document. I have to use the OBUFDS primitive from the unisim library. My final code contains the lines:

library unisim;
use unisim.vcomponents.all;

differential_pair_driver : OBUFDS
port map (
    O => ck,
    OB => ck_n,
    I => clk
);

Edit: What I didn't understand when I wrote this answer, is that the OBUFDS is a so-called primitive. The primitives you can use can be different for another FPGA. I think that in general, the most appropriate way is to look up the primitives for your specific fpga. I have a Spartan-6. Googling 'spartan 6 primitives' yields this document as the first result. The OBUFDS can be found on page 195.

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