Disclaimer: I am not sure if this is the right place to ask this.
I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron MT46H32M16LF or the Winbond W949D6CBHX6E, which operates the same way). The clock is transmitted using the differential pair ck, ck_n. In the constraints file for my design, the signals are defined as DIFF_MOBILE_DDR (while most other signals are defined as MOBILE_DDR: they don't seem to cause troubles).
My first try was to set ck to the clock, and ck_n to not(clock). However, I get the following error message in Xilinx ISE:
The I/O component "ck" has an illegal IOSTANDARD value. The IOB component is configured to use single-ended signaling and can not use differential IOSTANDARD value DIFF_MOBILE_DDR. Two ways to rectify this issue are: 1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O connectivity by instantiating a differential I/O buffer.
(and a similar message for ck_n)
My guess is that I have to use a differential I/O buffer. How can I do this is Xilinx ISE?
Googling didn't lead to much. A related question which seems to suggest that there is some HDL from a library that does what I want, but I still have no idea which one.