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I am reading "Rapid Prototyping of Digital Systems: SOPC Edition", and on p.113 it contains the following statement:

In VHDL, as in any digital logic designs, it is not good design practice to AND or gate other signals with the clock. Use a flip-flop with a clock enable instead to avoid timing and clock skew problems.

Could you explain what exactly are those "timing and clock skew problems", and give some contrasting examples of good and bad designs?

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Consider the case where you have some data that you want to latch into a register under some particular conditions:

simple flip-flop circuit

Here you would assert the gate signal whenever you want to save the data from flip-flop D1 into flip-flop D2 (maybe the D2 is a read buffer or part of a shift register, and a read transaction was just detected). However, meanwhile the input data to D1 may be changing.

The clock signal to the D1 happens pretty much as soon as the clock generator produces a rising edge. D2, however, doesn't see the clock edge until sometime later, due to the propagation delay through the AND gate.

If D1's state has changed, then D2 might latch in the new data, rather than old data you expected from your RTL simulation. Worse, depending on the clock-to-Q delay of D1 , the AND gate delay, and the flip-flop hold time, D2's input may be in the middle of changing when it detects the clock signal rising edge, causing its output to go metastable.

If, instead, you use a flip-flop with a clock-enable input,

enter image description here

you won't have this problem. Assuming the flip-flops have zero hold time (typical within FPGA's), there's no extra delay for the clock reaching D2, and the two flip-flops will sense the clock edge at (darn near) the same time. Then D2 will always see the "old" data from D1 as your RTL simulation led you to expect, and won't have a problem with metastability.

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  • \$\begingroup\$ (+1) Many thanks for the very clear explanation! \$\endgroup\$ – NPE Jan 11 '12 at 8:12
  • \$\begingroup\$ One approach I would think would be helpful in many cases, but which I've not seen discussed much, is having different latches triggered on opposite edges of the input clock. Clock-enables are cleaner than clock gating, but for low-power systems, I would think that gating a clock would save more power than disabling the latches the clock feeds. If the signal which gates a clock won't change anywhere near an edge of that clock, and if latches controlled by the gated clock will switch on the opposite clock edge from latches "before" or "after", are there any problems? \$\endgroup\$ – supercat Jan 11 '12 at 16:41
  • \$\begingroup\$ @supercat, within a chip (FPGA or ASIC) what your propose has at least two problems: 1. reduced amount of combinatorial logic that can be placed between two registers. 2. Imperfect duty cycle of the clock would further reduce the amount of delay you could tolerate in logic between registers. \$\endgroup\$ – The Photon Jan 11 '12 at 17:21
  • \$\begingroup\$ @supercat, on the other hand, for between-chip interfaces, what you suggest isn't uncommon. SPI normally works this way, for example. Difference is that between chips, the digital logic designer can't control the relative skew between the clock signal and data signals. \$\endgroup\$ – The Photon Jan 11 '12 at 17:23
  • \$\begingroup\$ I can see that input clock duty cycle could sometimes be an issue. On the other hand, for parts of a design that aren't running near maximum device speed, I would think that certain aspects of device verification could be easier, since one wouldn't have to worry about hold times anywhere--just setup times. Also, another issue I was wondering about: if a register's clock is fed by an "or" gate within an FPGA, and one input of that gate is high, could a change on the other cause a glitch on the output sufficient to trigger the register? \$\endgroup\$ – supercat Jan 11 '12 at 18:00
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The various signals and clock will have to pass through several devices, to achieve the desired logic function. These devices will have slightly different propagation delays, which will affect the timing of the signals, and will delay the clock slightly, skewing the edges relative to the other signals. At low clock speeds these effects are unlikely to cause problems, but they could result in a high-performance system failing to operate properly.

I've got the Quartus II edition of that book, BTW.

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    \$\begingroup\$ There is the possibility of hold time violations, which can ruin your day at any clock frequency. The more skew in your clock, the bigger your nightmares (at least in SoC's) \$\endgroup\$ – W5VO Jan 10 '12 at 14:28

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