I created this circuit in an app I have on my phone that runs the circuit and lets you see the output.
So, I went about trying to design create a NAND based SR latch first, which would serve as the core of my JK circuit, in making the SR latch I believe I accomplished by adding a second NPN transistor in series to a NOR Gated SR design. but looking at the JK flip flop diagram, it looks like I need to add two more NAND gates. I believe the gates will output to the emitters of S and R of my latch, and for each of the new NANDS they will be tied into the SR by the transistor base. I hope that is correct. However, I'm not clear on how to physically create a NAND gate with 3 inputs. I am going to create a circuit lab diagram of what I think I need to add. And I'll attach it shortly, but I wanted to see if I truly understand this.
So, I've learned A LOT today. I spent several hours online pouring over diagrams and articles I barely understood. And looking at my above circuit I realize I made a lot of mistakes. One fundamental thing I learned was that gates are binary, and so a single gate represents 1 bit and can only be 0 or 1, so...the total number of gates will be equal to the number of bits needed to express the number of inputs. Since I wanted a 3 input NAND for my J and K, I needed to cascade 3 NAND gates since 3 is 001 in binary. So, I just finished creating that in circuit lab. Also, I think I now understand that the symbol used for all logic gates do not try to display Vdd or V0, they are assumed. Now, all I have to do is duplicate the NAND gate four more times, cross couple two of them and I should have my own JK flip flop!
Additionally, I went through the tedious task after making my 3 input NAND and verified every row in the truth table using a spice simulator.
The circuit is below. I haven't tested it to verify, and due to not being able to mirror the parts I'm not sure if I have all the inputs tied together correctly.
Any input would be appreciated.