I am designing an SPI system with one master and two slaves. In a normal SPI system, the master needs 2 outputs to control the slaves' chip select lines. I want to use only one output to drive both chip selects thanks to a classic NOT gate.


simulate this circuit – Schematic created using CircuitLab

I haven't tried this yet because I see one issue:

  • When the master command comes from HIGH to LOW, both chips will be selected for a short time due to the NOT gate delay.

Can this issue cause an overall problem?


For this easy scenario, a "not" gate does the job, what is commonly used when there are many more slaves? MUX?

  • 1
    \$\begingroup\$ On your edit - For more than two you could either use a mux, a shift register or some form of latch depending on the situation. A mux is easier and probably the best system for up to 8 devices. More than that and the mux is going to need 4 or more pins, other systems would use less pins but be slower and more complex to implement. As with the 2 device situation you would need to be careful on the timings and sequencing when switching between devices. \$\endgroup\$
    – Andrew
    Commented Apr 27, 2017 at 9:09

3 Answers 3


If you really only have two devices, this can work if you're careful. Some points to consider:

  1. Make sure to switch the slave select line only between full sequences and with some dead time before and after you try to transfer data.

  2. Many chips use the leading edge of SS to reset their logic to the start of a new sequence. Even if you are using the same chip several sequences in a row, you will have to de-assert its SS between sequences. This means the other chip will see its SS asserted for short blips. That should be OK, but again, make sure this is only happening when the data and clock lines are quiescent.

  3. The low level firmware may need to do a extra SS pulse to guarantee that the target device sees the leading edge of SS, not just SS asserted at the start of a sequence.


In addition to points already noted, do check that all the chip-select timings on both devices will always be met. It's easy to remember to check chip-select timings for the chip you're selecting, but forget the timings for the chip you're unselecting. Many SPI chips need a minimum time between the last clock edge and chip-select disabled.


It should do the trick in most cases. But I think it's a bad idea to switch between slaves while the interface is active, so you should treat this issue in the master's software : let's assume slave 1 is selected. You should first stop communicating with it, then switch to slave 2, then start communicating.


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