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I will connect an ADS4125 12-bit 125-MSPS ADC with 6-bit parallel DDR LVDS output, with an Altera MAX10 FPGA. The sampled data is over a duration of 100 us, and will be filtered in the FPGA. I will use the FPGA LVDS interface to convert the 6-bit DDR to 12-bit synchronous, store it in either a FIFO or a RAM, do signal processing on the data, save the result as a number of flags (not saving the post-DSP data), and output the unprocessed data along with the flags to a radio.

I am leaning towards using a 2-port ADC over a FIFO, because I will need the unprocessed data twice.

I wonder however, would there be advantages to using a FIFO?

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In most cases I would say a FIFO is preferred. Why?

Because I am assuming (as it is in most cases) that the core clock is different from the ADC clock. The dual clock FIFO solves synchronization between reads and writes for you.

If you use dual port RAM, you will have to invent by yourself the write address vs. read address synchronization mechanism.

Even if you have to process the data twice, I would use a dual clock FIFO and open two paths for processing on the core clock side.

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  • \$\begingroup\$ The RAM inputs and outputs are registered using the core clock. There are two address registers, and the RAM can be written and read simultaneously, even to/from the same address (the read will return the previous data value). \$\endgroup\$ – Jacob Jul 29 '16 at 13:04
  • \$\begingroup\$ The snippet about write/read address synchronization is enough to convince me that FIFO(s) would be easier. \$\endgroup\$ – bornruffians Jul 29 '16 at 13:07
  • \$\begingroup\$ I actually ended up going with an Altera IP 2-port dual-clock RAM, hvis works great and takes up half as many memory elements as a FIFO + RAM (I need the RAM). \$\endgroup\$ – Jacob Aug 4 '16 at 16:05

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