I started creating a scheme for 8086 based computer now I'm in trouble with memory addressing. I know a 20 bit wide addressing line can address up to 1024 KB of RAM and that pin A0, when high, select all the even memory banks and when BHE is high the odd memory banks are selected (yes I know there is a bit more complicated logic circuit to do this).
I choosed a setup where there are 8 chips (6x 128 KB are SRAM chips and remaining 2x 128KB are EEPROM chips).
Reading online I know that using a M74HC138B1R (a so called 3:8 decoder) I need to use A17, A18 and A19 to decode what chip select, ending having the lines A1-A16 to use for chip addressing. The problem comes when according to IS62C1024AL datasheet (chip I wish to use as SRAM) the chip use 17 lines for addressing (A1 up to A17) meaning 17 bit=128KB. But doing this I end up with 1 address line in conflict (A17).
I can't figure it out how to exit this weird situation and I can't figure it out if the A0 still available for addressing, my assumption following the logic is no. Another thing that seems obvious to me was searching for a 2:8 decoder that apparently it doesn't exist.
Any tip is much appreciate, may be I'm currently missing something stupid I can't figure it out now.