# 8086 memory decoder logic

I started creating a scheme for 8086 based computer now I'm in trouble with memory addressing. I know a 20 bit wide addressing line can address up to 1024 KB of RAM and that pin A0, when high, select all the even memory banks and when BHE is high the odd memory banks are selected (yes I know there is a bit more complicated logic circuit to do this).

I choosed a setup where there are 8 chips (6x 128 KB are SRAM chips and remaining 2x 128KB are EEPROM chips).

Reading online I know that using a M74HC138B1R (a so called 3:8 decoder) I need to use A17, A18 and A19 to decode what chip select, ending having the lines A1-A16 to use for chip addressing. The problem comes when according to IS62C1024AL datasheet (chip I wish to use as SRAM) the chip use 17 lines for addressing (A1 up to A17) meaning 17 bit=128KB. But doing this I end up with 1 address line in conflict (A17).

I can't figure it out how to exit this weird situation and I can't figure it out if the A0 still available for addressing, my assumption following the logic is no. Another thing that seems obvious to me was searching for a 2:8 decoder that apparently it doesn't exist.

Any tip is much appreciate, may be I'm currently missing something stupid I can't figure it out now.

• "Need" is such a strong word. Vcc and GND are always available as 1 and 0 respectively. – Ignacio Vazquez-Abrams Jul 29 '16 at 14:00
• A17-A19 -> 74HC138 which gives 8 outputs - 6 for SRAM, 2 for EEPROM; A0-A16 will be a bus – Flanker Jul 29 '16 at 14:01
• @Flanker Unfortunately A0 is not available. The chips he has are 8-bit, and the 8086 is a 16-bit data bus. The OP has to use A0 as a selector between High and Low chips, as he said in the first paragraph. – John Burger Jul 29 '16 at 14:29
• My bad, now I see why BHE# is important. Quick search reveals that A0 is still used: combination of BHE# and A0 both LOW shall address 16 bit wide data (otherwise 8 bit data, for 8080 compatibility I guess). It seems you should organize all memory into 2 logical banks; above address decoding is still valid; only additional logic must be implemented to select lower bank (8 bit data), upper bank (8 bit data) or both banks (16 bit data) – Flanker Jul 29 '16 at 14:42

Your problem is that you talked about using Banks of RAM in your first paragraph - but then assumed you would use the chips serially.

You should use the chips in pairs, using A0 and BHE as you described. So you actually have a 2x3 array of RAM chips and a 2x1 array of EEPROM.

There is no such thing as a "2-to-8" decoder precisely because you need 3 bits to get 8 possibilities - but you need a 2-to-4 decoder:

• A19-A18 to decode which pair of RAM or EEPROM chips;
• A17-A1 to decode the address in each pair;
• A0 and BHE to decode which chip in the pair.
• I'm a bit embarassed. When I thought about 3:8 and 2:8 I didn't think about 3 bits producing 8 possibilities and so it's clearly that I will need 2:4 to produce 4 possibilities, 4 blocks where 3 are RAM and 1 is ROM. Thanks that you cleared the dust from the neuron holding that information. – Gioele Frapolli Jul 29 '16 at 15:16
• little clarification: "A0 and BHE to decode which chip in the pair".. or both chips in pair – Flanker Jul 29 '16 at 15:29

The 8086 has a 16 Bit wide data bus. You need to combine 2 (8 bit wide) chips each, and wire A1-A17 on 8086 to A0-A16 on the chips.

A18 and A19 are to be decoded for chip selects. You can use a 3-to-8 decoder here, just wire one input pin to GND or VCC.

Looking at the pinout of the 8086 it seems to use multiplexed data/address lines. This means you need to use latches, and you may need to "byte swap" the data when address bits A0 or BHE are set using some additional logic chips.

• Thanks for your answers, all answers for me are gold. Said that I know that A0/BHE require more logic than putting simply connect them to memory chip. – Gioele Frapolli Jul 29 '16 at 15:09

This simply comes from the fact that IS62C1024AL has an 8-bit bus. Whereas the 8086 has a 16-bit bus. So the RAM chip needs 17 address lines, but a 128k zone from the 8086 is adressed using 16 address lines only (plus A0 and BHE to select between high and low bytes).

Here is what you need to do: divide your memory into 4 big areas (determined by A18 and A19), not 8 areas. So you have A18 and A19 that go to a 2-to-4 decoder that will provide the chip selects. Then you have A17-A1 that go to the address lines of each memory chip.

Then group the memory chips in pairs. For each pair, the first memory chip will be wired to data bits 0-7 of the CPU and the other to data bits 8-15. So you have four groups (determined by chip select) of two memory chips, each chip connected to either the low or high part of the data bus. In total, you have your 8 chips of 128k, providing a total of 1Meg. All fine.

This means the chip select (from the decoder) of each of the four groups will be provided to both memory chips of the group. Let's call it the primary chip select. Then you need to use A0 and BHE as a secondary chip select to enable/disable each of the two memory chip of the group. And, guess what? By chance, the IS62C1024AL have two chip select pins.

To sum up: use a 2-to-4 decoder that will feed CS1 of both memory chip of each group, feed the CS2 of all the low-byte memory chips from A0, and the CS2 of all the high-byte memory chips from BHE. Now, if you look at the details, you'll see you probably need some additional inverters, unless you find a decoder with active high outputs.

Last advice: The glue logic is not that simple, especially since the 8086 uses a multiplexed bus. A mistake is always possible (I don't even pretend having given the correct answer). And the 74 logic chips are not all easy to find, are bulky, and if you made some mistakes, you'll need to relayout, etc... If I were you, I'd use some CPLD to make the whole glue logic. Then you can really reconfigure things easily in case of mistake, or if you suddenly want to change the hardware configuration. You could even build a few simple peripherals (GPIO, keyboard, ...) within the CPLD itself. It's much more fun than soldering/desoldering/rewiring/soldering/... DIP chips.

• I know that I may be had to pair the RAM/ROM by 2 in 4 groups where 1 chip is even and the other one is odd and then select them by using A0/BHE but I was missing, as said before a dumb thing, the 2:4 logic which I wrongly ended up calling it 2:8 while searching on internet. About multiplexed I already knew that and I have latches and transcievers to do demultiplexing. The last thing you said is my last resort since I have many of the required components and the local refurbisher have the logic 74 chips. – Gioele Frapolli Jul 29 '16 at 15:06