I have 8 layers: 2 ground planes, 4 signals layers and 2 to route power. When planning the vias, I was thinking of not using through vias for my FBGA packages. Decoupling capacitors etc. placed on the bottom layer clash with the through vias. Instead I am planning to use multiple vias to go from top to bottom layer using at least one intermediate layer based on whether its power or signal.

Is that the correct way to do it?

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    \$\begingroup\$ Are you planning vias before routing o_O? \$\endgroup\$ – Eugene Sh. Jul 29 '16 at 18:57
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    \$\begingroup\$ I was always thinking of the vias as a part of the routing which are added on demand. \$\endgroup\$ – Eugene Sh. Jul 29 '16 at 19:03
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    \$\begingroup\$ It depends on the technology available. You can use so-called "blind" vias, which are not "penetrating" all of the layers, or the full through vias, which are simpler to manufacture. If you can use the simpler solution, you will avoid some troubles with manufacturing and testing. \$\endgroup\$ – Eugene Sh. Jul 29 '16 at 19:07
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    \$\begingroup\$ "FBGA"? As in Ball Grid Array, or a misspelling of "FPGA"? \$\endgroup\$ – FiddyOhm Jul 29 '16 at 19:23
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    \$\begingroup\$ If you're considering blind vias, contact your PCB fabrication vendor first. You need to determine what they can support; blind vias may be smaller laser-drilled holes that can only penetrate outer layers. If your design exceeds their manufacturing limits then it will be wasted effort, so make sure you understand what they are capable of fabricating. \$\endgroup\$ – MarkU Jul 29 '16 at 20:58

"Is that the correct way to do it?"

The "correct" way to do it is the way that works! "Works", in turn, can be a multi-dimensional term. Since you are doing this layout as an academic exercise some of these dimensions of "work" will probably not matter.

So, Dimension 1: Connectivity. If all you need to do as part of this exercise is make all of the electrical connections on the board correctly (i.e. according to a schematic, or net list), your via scheme will be fine.

If you were making a real-world PCB these other dimensions would likely play a critical role:

Dimension 2: Solderability. The integrity of the solder joints produced between a large ball count BGA package and its footprint is largely dependent on the thermal characteristics of the overall footprint geometry. Ball pads that are routed to inner layers will tend to loose heat to the inner layer during the vapor solder operation, resulting in a relatively cool pad, and thereby a cold solder joint for that ball. Those pads connected to a thin signal trace will tend to get hotter during the solder process and react oppositely - either getting the correct amount of heat to form a good solder joint or overheat causing the solder to bubble and create a void in the joint.

So, that recommended footprints and routing for a BGA are often based on their expected thermal performance during the soldering process. I have seen footprints which had a via per ball. The goal here was to achieve uniform heat distribution during the soldering process throughout the array, even though all of the vias were not connected to signals or power planes.

Dimension 3: Signal Integrity. The frequency of the signals in your circuit may require impedance matching and/or balancing if they are differential signals. The inclusion of vias in these so-called "high speed traces" can be quite troublesome to the goals of impedance control.

Further, the routing of the signals to avoid noise generation and noise susceptibility is also an issue in real-world PCBs that will likely never be known in an academic exercise.

Dimension 4: Voltage Distribution. Making sure every package gets the correct operating voltage(s) can be challenging. I've participated in designing high speed communication PCBs in which the ICs drew many amps of supply current. The IR and IL drops of the planes, traces, and vias all worked against this requirement at such supply current levels. This is another performance criteria that may never come to light in an academic PCB layout exercise.

Dimension 5: Thermal Performance. Aside from the thermal issues associated with solderability there are those associated with actual operation. Here you are concerned with getting die-generated heat away from the IC packages. The inner planes play a large role in this by conducting heat away from the ball pads. Where you have multiple ICs, you will want to space them far enough apart that the heat from one doesn't contribute to the overheating of a neighbor.

In summary, if your academic PCB layout will only be judged on connectivity, your summer should be relatively enjoyable. However, don't expect a "vacation" when you get to laying out such a complex PCB in the Real World of Electrical Engineering.

  • \$\begingroup\$ So, I'm sticking to dimension 1 for now and going ahead. I can revisit the rest of the dimensions when I proceed with more understanding. I like the answer more cause you also used my "summer vacation" part. \$\endgroup\$ – Harshad D Jul 29 '16 at 21:44

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