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What actually has to happen, at a pins and signals level, to program a GAL device? Let's say I have a GAL 22V10, and a .JED file with the desired fuse pattern. The usual way to proceed is to drop the chip into a commercial programmer, load the .JED file, and tell it to go. But what goes on to configure the chip? How are those 'fuses' specified? How are they read back, written, erased?

After some effort with search engines, I don't have anything more concrete than 'PALs are programmed similar to PROMs' to go on. The implication seems to be that if you have a PROM programmer, it doesn't take too much to program a PAL or GAL. Does this mean that with programming voltage applied, you can address the fuses like a memory? Of course GALs are erasable and PROMs were not, so this analogy says nothing about how you'd go about erasing one.

In particular, the project at http://elm-chan.org/works/pgal/report_e.html makes it evident that the hardware is very simple; the only interesting bit being the software to control it. Unfortunately (for me) the commentary in the accompanying software is in Japanese, and the code itself is in 1980's style macro assembler for DOS, so teasing out the protocol looks daunting, as the code to read the .jed file (using DOS-isms) is all mixed up with the programmer I/O. (Not to mention he has his own protocol layered on top, to shift all the parallel bits through those 595s)

And yes, I know the 22v10 is a dinosaur. Let's say I just want to know.

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  • \$\begingroup\$ This looks like a starting point: armory.com/~rstevew/Public/Pgmrs/GAL/algo.htm \$\endgroup\$ – The Photon Jan 11 '12 at 0:22
  • \$\begingroup\$ @ThePhoton - very useful. Looks like internally the 'fuses' are organized into a number of shift registers, with a 6-bit input to select which line responds to the SDin/SDout pins. \$\endgroup\$ – JustJeff Jan 11 '12 at 2:28
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My recollection is that they were programmed using parallel addressing and this page on TI's website would seem to confirm this.

Not all PALs are eraseable btw. AMD & Lattice's PALCEs are electrically eraseable (the standard PALs were not). I don't know about TI's TIBPAL & TICPALs I linked-to but the programming docs make no mention of erasing.

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    \$\begingroup\$ Yeah, I think the standard PALs like the 16R8 etc used actual fusible links, and were one-time programmable, whereas the later GAL chips were EEPROM based and could be erased. The TI docs were a good find, but seem to cover PALs only, though still doubtless informative about the general programming approach. \$\endgroup\$ – JustJeff Jan 11 '12 at 12:00
  • \$\begingroup\$ And then there were the EPROM versions. How many programmers do you know who would be productive under conditions of 90 minutes under the UV light for each recompile? Used some of those in an undergrad electrical engineering course. \$\endgroup\$ – Ben Voigt Jan 11 '12 at 19:41
  • \$\begingroup\$ @BenVoigt: Most people I've seen using EPROMs would almost always try to have at least two parts in rotation, if not three. Having four or five was even better, because you could hold off on erasing your previous version until you were sure you wouldn't want to use it again (e.g. if you put in the new chip and nothing works, it may be helpful to re-confirm that everything else in the system is still good). \$\endgroup\$ – supercat Nov 3 '13 at 20:49

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