I'm trying to build a frequency divider on a Lattice iCEstick using Verilog (with yosys, arachne-pnr, and icepack/iceprog):
module demo(input clk, output LED1, LED2, LED3, LED4, LED5); assign LED1 = state; // Generate impulse at lower frequency: wire out_clk; reg [31:0] cnt; initial cnt <= 0; always @(posedge clk) cnt <= cnt >= 6000000 ? 0 : cnt + 1; assign out_clk = cnt == 0; // On impulse, toggle state: reg state; initial state <= 0; always @(posedge out_clk) state <= ~state; endmodule
This works as expected, i.e. the LED on the board blinks about once a second (the clock is 12MHz).
However, when 6000000 ('h5B8D80) is replaced with 5000000 ('h4C4B40) the LED simply stays on permanently. Why is that?
Simulating with Icarus shows the expected state changes, no matter what the divisor is.
Here is a table of experiments with more values:
'h5B8D80 blinking 'h5B8D7f permanently on 'h5B8D7e blinking 'h5B8D7d blinking 'h5B8D7c blinking 'h5B8D78 blinking 'h5B8D70 blinking 'h5B8D60 blinking 'h5B8D40 blinking 'h5B8D00 blinking 'h5B8C80 blinking 'h4C4B40 permanently on 'h400000 blinking
Also, for 'h4C4B40 adding the line "assign LED2 = 1;" makes LED1 (!) blink as expected. This is not the case for 'h5B8D7f.
Altogether, the behaviour seems wildly random.
EDIT For the record, when synthesizing the same design with Lattice's iCEcube2 the problem doesn't occur.