I've just begun the MOS-level study of a MOSFET. So, pardon the naivety.

A very brief backstory: The Strong Inversion occurs in a MOSFET, particularly NMOS, when the silicon surface reaches a voltage value which is twice the Fermi Potential(ϕ). For p-type silicon, ϕ= -0.3V. Hence, for the inversion to occur the silicon surface voltage should reach -0.6V, given that voltage between source and body (Vsb) = 0V. The Value of Vgs (gate-to-source voltage) where strong inversion occurs is called threshold voltage (Vt).

My question: Please refer to the figure, which is mentioned in the same context as above. It says at Vbs = 0V, the value of Vt = 0.45V. So, at a gate voltage of 0.45V, inversion occured, which essentially means that the silicon surface potential has reached -0.6V.

With just an external gate voltage of 0.45V, and all other potentials (Vsb) at 0v, how did the silicon surface manage to attain a voltage of -0.6V. Where did the extra voltage come from? My question might be wrong as well, owing to the feeble intimacy to the topic; I tried others books but couldn't find a clean answer. Please enlighten.

enter image description here


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Here is how I would analyze the threshold voltage. This is the short answer. I can elaborate, so feel free to put suggestions in the comments. I want to make a few notes first.
There are a few ways to define the threshold voltage that I have seen. When you have access to the devices, you do not know the doping so you cannot know where the exact Fermi levels are. When you are just pushing through the physics you make assumptions about what the dopings are, which differs in practice. Now back to the "textbook" approach:

I present to you an nFET that looks as follows: enter image description here

In the image, \$\Phi_s\$ is the surface potential and \$\kappa\$ is the channel divider and this term is what relates to your graph, and I define this as $$\kappa=\frac{C_{ox}}{C_{ox}+C_{dep}}$$ Deriving the threshold for the simplest condition from first first principles (no charge sharing on the sides), you should get the following (corrections welcome):

$$V_{T0}= V_{FB} + \frac{V_{BG}}{\kappa} +\frac{2 U_T}{\kappa} \ln\left[\frac{N_D}{\sqrt{N_C N_V}}\right],$$ where \$U_T\$ is the thermal voltage, \$V_{BG}\$ is the band-gap, and \$N_C\$ and \$N_V\$ are the density of states for the conduction and valence bands respectively, for temperature these are fixed. \$V_{FB}\$ is the flat band condition and this will change depending on the "junk" in your oxide, and this is your lumped offset, which is the extra voltage you are eluding to.

The change in the divider,\$\kappa\$, to the surface is what is causing your threshold shift in the graph. (I can also tell you that device was very small, probably a DIBL device to get behavior like you see in the graph. )


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