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I've got a circuit using two dual opamp ICs and one voltage reference (see schematic below). I have a dual supply and use one of the opamps to create a low noise negative reference. The other opamp IC uses these two references. I have a simple follower and a differential amplifier implemented in this second IC.

The problem is that the follower doesn't follow(??). Any ideas about why this isn't working? I'm pretty sure its not a wiring problem since its actually on a PCB created from the schematic below and I've checked it pretty thoroughly. enter image description here

Edit:
A couple people noted some odd/wrong things with my schematic. The image above is sub-circuit pulled from the one shown below.
enter image description here

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  • \$\begingroup\$ First thought: Op-amps don't like capacitive loads. C19 and C20 may be causing IC1 (generating V-) to oscillate, so that the power provided to IC2 is not stable. Second thought: What is the point of using IC1 to buffer ground? Ground itself is a better reference for ground than the output of IC1. \$\endgroup\$
    – The Photon
    Jul 31, 2016 at 1:58
  • \$\begingroup\$ Third thought: if you give each component a different designator (like IC1A and IC1B) it would be easier to talk about your circuit. \$\endgroup\$
    – The Photon
    Jul 31, 2016 at 2:03
  • \$\begingroup\$ I'll try desoldering the caps. Also I was wondering if anyone would be bothered by the random ground buffer :). It actually is designed to have an input but I grounded it for this test. Thanks, for the tip on the schematic. Its actually the first one I've shared so it was nice to get a comment on it. \$\endgroup\$
    – PantsMachine
    Jul 31, 2016 at 2:12
  • \$\begingroup\$ None of my points really points directly to your problem, though. Like anther comment said (now removed) also double check the solder joints on IC2. \$\endgroup\$
    – The Photon
    Jul 31, 2016 at 2:17
  • \$\begingroup\$ As pointed out by @ThePhoton, there are numerous design errors, the kind that make op-amps behave erratically at best, or burn up at worst. No chance of an answer until these serious design bugs have been fixed, then update your schematic. \$\endgroup\$
    – user105652
    Jul 31, 2016 at 2:39

1 Answer 1

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There is no dot closing the feedback loop on U$4G$1, so you think you have connected something that isn't connected. Eagle puts dots at every junction, and one is missing here. Go into eagle, and move around some nets to convince yourself this is true. Use a wire to connect pins 1 and 2 to close the feedback loop. I bet you'll see that the inverting input and the output are on different nets. Use the eyeball tool is the schematic to look at traces on the board as another easy way to check.

There may also be an issue with OUTS on the gate in the upper left corner.

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  • \$\begingroup\$ Thanks for the reply. The errors you point to are actually bad presentation on my part. I cut down a larger schematic to show just what I had connected. I made an edit to show what the original is. \$\endgroup\$
    – PantsMachine
    Aug 1, 2016 at 0:35
  • \$\begingroup\$ @PantsMachine Too complex for me. Can you show the actual layout on that chip? It's pretty clear that you have no feedback or your outside the common mode input requirements. \$\endgroup\$
    – Scott Seidman
    Aug 1, 2016 at 2:01

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