I had finally finished my Z80 memory board, but I was disappointed to see that it wasn't working properly (simple NOP test with the address lines connected to some LEDs) as the counter quickly spiraled out of control instead of incrementing as it should. However, I am not one to give up and after about thirty minutes of continuity testing to unveil no short circuits and all proper connections, I finally thought to check if the SRAM chip was powering on with all 0s stored. I am well aware that SRAM (unless non-volatile, which my particular chip is not) will lose all of its contents upon losing power, but I had always assumed that it would be filled with 0's (ie "empty") when it regained power. The SRAM I'm using seems to be randomly filled with 1's and 0's each time the power is reset. It never remembers any data, but it isn't loading empty. This isn't really a problem as I can simply write a small program in ROM to load all 0's into RAM on powerup, although I would still like to know if this is how the SRAM should be functioning or not. Thanks!

Edit: I forgot to mention that after using the ROM to load 0's into SRAM the system worked fine, so this was indeed the issue.

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    \$\begingroup\$ You can use SRAM power up to generate random numbers. This is generally how we do it if we only need one random seed. \$\endgroup\$
    – b degnan
    Commented Jul 31, 2016 at 20:32
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    \$\begingroup\$ @bdegnan Once, maybe. The power-up state of SRAM tends to be somewhat predictable for any given part. \$\endgroup\$
    – user39382
    Commented Aug 1, 2016 at 2:13

3 Answers 3


Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's.

SRAM memory stores memory on back to back inverters.

simple sram

This forms a bi-stable system (two very stable states with metastability dividing them). So, upon power up the back to back inverters are briefly metastable.

This happens because as the voltage ramps up (from being turned on), both NMOS and PMOS of the back to back inverters would be 'equally' on, holding both bitnodes at half the supply voltage (this is the metastable state). Eventually some thermal noise (or any process that introduces variation) pushes or pulls this value down or up a little bit. At this point the bitnodes snap into one of their bistable states.

  • As an example, consider \$ Q=Q'=\frac{V_{supply}}{2} \$
  • Next, some thermal noise on Q increases the voltage up to \$ \frac{V_{supply}}{2} + \delta \$
  • Now, the NMOS feeding Q' gets turned on just a little bit more. And the PMOS feeding Q' gets turned off just a little bit more. So Q' pulls down from \$ \frac{V_{supply}}{2}\$ to \$ \frac{V_{supply}}{2} - \delta \$.
  • Next, since the voltage at the gate of the FET's driving Q node decreases, the PMOS turns on a little more (and NMOS turns off more). This causes Q to increase further to the supply. And this quickly snaps Q' to 0 and Q to 1.

In fact, there is even a paper "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers"

One very helpful plot contained in the paper is below. The dotted line represents the supply voltage ramping up:

metastability at powerup

  • On the left-side, everything is equal. In this case, random variation due to temperature or another number of factors bumps the bitnode into one state or the other.
  • On the right side, there is a bitnode which is skewed (purposefully or otherwise) to be much more likely to initialize in a particular state.

Depending on how each bitnode in the SRAM you are using currently was fabricated, you end up with more or less of one of the two situations above. In both cases, unless you intentionally skewed the SRAM, the initial outputs would look more or less random. In the left-hand situation, each subsequent powerup would generate more random patterns. In the right-hand situation, the initial startup would be seemingly random. But further powerups would cause the SRAM to tend to further certain states.

  • \$\begingroup\$ You know I actually thought that would be why it was loading randomly. I've used a NOR latch as part of a circuit and it would reset randomly on power-up. Thanks! \$\endgroup\$
    – KeatonB
    Commented Jul 31, 2016 at 18:18
  • \$\begingroup\$ I thought you could design SRAM chips so that they power up in a known state. Can you? \$\endgroup\$ Commented Aug 1, 2016 at 5:42
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    \$\begingroup\$ @JanDvorak: Yes, you can. But that doesn't mean it is commonly done, esp in SRAM that is not application specific. I would think it costs more and for what purpose? It will rarely be the same initial state required across consumers. \$\endgroup\$
    – jbord39
    Commented Aug 1, 2016 at 5:54
  • \$\begingroup\$ @jbord39 Could this help me bake the bootloader into the memory, and avoid having an extra ROM chip to load the OS from? Would it help cut down the costs? \$\endgroup\$ Commented Aug 1, 2016 at 5:56
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    \$\begingroup\$ @JanDvorak: For specific applications the bitcells could be skewed or biased to start up in specified states. But really the cost is not worth it, because each customer would need different initial states. It is far easier and cost efficient to just initialize it with external circuitry (such as ROM). I guess they could build in some programmable circuitry to allow you to burn in your desired initial states, or some other scheme. But this just sounds expensive when you clearly already have the circuitry to write/read to the RAM. So, just write your desired state. \$\endgroup\$
    – jbord39
    Commented Aug 1, 2016 at 6:05

Having worked with SRAM for many years, I can tell you that it will power up with seemingly random contents, although I have seen devices that power up with nearly the same random looking contents each time. If the power off cycle is short enough (depending on power supply characteristics and the number & value of bypass capacitors), large fragments of previously written data can linger in the SRAM through power cycles - although the content will be corrupted.


A single bit is stored in a SRAM in a circuit of 6 or more transistors. If you want a defined power on reset behaviour for the SRAM, each RAM cell would need more than 6 transistors only. The needed chip area will be substantially larger and the SRAM chips will be more expensive. This is a parallel power on reset of all bits at the same time. A serial reset would require an oszilator, an address counter and enough time during power up to resets all RAM bits or bytes sequentially. If the processor accesses the SRAM before the serial power on reset is finished, errors may occur and data may be lost or changed.

There are programming environments for microprocessors with detailed memory mapping of several RAM areas. You may define an area with or without a power on reset as required by the application. Several different areas within the same SRAM are possible. It is not always necessary to reset the whole SRAM on programm start.

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    \$\begingroup\$ Making some of the transistors slightly larger than others would skew the probabilities of ones versus zeros. On many parts, the transistors will be balanced to within manufacturing tolerances, meaning that some bits will be biased toward zeroes while others will be biased toward ones. I doubt the size differences would need to be very large to bias the startup behavior overwhelmingly in one direction; RAM makers could easily bias things consistently if there were any reason to do so, but a RAM which is imbalanced would consume extra current to switch the cell to the disfavored direction. \$\endgroup\$
    – supercat
    Commented Aug 1, 2016 at 16:55

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