# Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" or not. During the class of my supervisor, I had a small example showing how I can build a 8 bits LUT with smaller LUT and multiplexer. I have to do the same things but with a concrete FPGA.

I have looked the datasheet of the Altera Cyclone V and I have found that they use Adaptative Logic Module instead of "simple" Logic Element. However, when I want to check the number of logic element used by this 8 bits LUT, the answer is given as Logic Element. At this point, I have several questions :

• In this file, it is written that 2 4 bits independent LUTs can be implemented in one ALMs. Does it mean that 1 8 bits LUTs can be implemented in an ALMs ? If not, how many ALMs are needed ?
• When I set only one LUT in my design and compile, the number of Logic Element used is 34. This number is a little bit unexpected since I have read that an ALM should be equivalent to 2 Logic Elements. Is that correct ? In this case, does this value seem correct ?

EDIT :

To help you, this is the code of my element (I have removed lines such that the post stays clear) :

module sbox_lu(input logic[7:0] in,
output logic[7:0] out);
always_comb
case (in)
'h0 : out = 8'h20;
'h1 : out = 8'h8d;
'h2 : out = 8'hb2;
...
'hfc : out = 8'h53;
'hfd : out = 8'hb4;
'hfe : out = 8'h6;
'hff : out = 8'hfe;
endcase
endmodule


As duskwuff suggested, this is some screenshots of the chip planner : i.stack.imgur.com/WCXL3.png

i.stack.imgur.com/WzX7p.png

The first picture is a "global" view of the chip. We can see that 5 LABs are used. If I zoom on the right top group, I get the second picture. In the left bottom LAB, only one ALM is used. If I go back to the second picture, we can see that 33 ALMS are used. If I add the one of the bottom group, I get the 34 ALMs. When I click on the used ALM, I can see the path and that each ALM can be seen as a 6 LUT. If I refer to the previous document, I would need 4 ALMs for the 6 LUT and 3 2:1 multiplexer to handle the last 2 bits. In this way, I don't really understand why 34 ALMs are used. In addition to that the ALM of the left bottom LAB is empty.

In this file, it is written that 2 4 bits independent LUTs can be implemented in one ALMs. Does it mean that 1 8 bits LUTs can be implemented in an ALMs ? If not, how many ALMs are needed ?

No. Refer to Figure 6 on the PDF you linked (page 7). A single ALM contains two LUT4s and four LUT3s. There are only 64 bits of configuration "state" in these six LUTs -- 16 in each LUT4 and 8 in each LUT3 -- so it's impossible to use them to emulate anything larger than a LUT6 in the general case. As noted in Table 1 (page 2), there are some special cases where it may be possible to emulate a larger LUT, but these cases depend on the LUT contents having certain specific structures.

When I set only one LUT in my design and compile, the number of Logic Element used is 35. This number is a little bit unexpected since I have read that an ALM should be equivalent to 2 Logic Elements. Is that correct ? In this case, does this value seem correct ?

Hard to say exactly without a lot more details on the design you're implementing, but there are a few possibilities that occur to me:

• Are you looking at an exact count of logic elements, or is it estimating a number of "logic cells"? The latter is an inexact estimate of the number of 2-input logic gates that would be needed to synthesize a design, and as such is expected to be much higher than the number of LUTs or LEs used.

• The fitter may have opted to not pack your design into a single physical LE, either because splitting it up may have helped with routing and timing, or because you've pulled out an intermediate signal that wouldn't be available in a single-LE layout, or even just because Quartus just didn't feel like it that day. (FPGA software can be fickle like that sometimes.)

Viewing the exact physical design that's been implemented in the Quartus Chip Editor may be instructive.

• One ALM can perform some 7-input LUT functions. – Tom Carpenter Jul 31 '16 at 19:36
• @duskwuff This is what I expected. Considering the number of logic elements, I focus on the "simple" element such as a 8 LUT. I have implemented this one as a simple switch statement. As I explained in my question, my goal is to find an expected number of logic element and check that the number I have is equal or very different. I'll check the Quartus chip editor (I don't have my Windows laptop right now) :) – user1382272 Jul 31 '16 at 21:24
• @TomCarpenter Right, that's what I'm alluding to when I mention "certain specific structures". – duskwuff -inactive- Jul 31 '16 at 23:32
• I have added picture and code – user1382272 Aug 1 '16 at 8:38

Ok, I get the answer :) In practice, with one ALM, it is possible to implement a 6 entries LUT. Since I need to build a LUT with 8 entries, I have to used 5 ALMs : one ALM taking the 2 last entries and the outputs of the 4 others ALMs. The other ALMs take the 6 other entries. Since one LUT 8 entries will output one bit, I need 8 LUT with 8 entries to output 8 bits, which means that I need 40 ALMs theoretically. However, two output bits doesn't depend on the 8 input bits but on less, which gives the right number :)