I am finding it confusing in defining various clock domains in the design. I did search over the Internet but I didn’t get a complete clarity on this.

In a certain FPGA (Actel ProASIC series) based design, I am generating three clocks – 48MHz, 24MHz, and 12MHz from an 8MHz crystal input using a PLL. Further, using one of these 3 clocks (48/24/12) I have to generate 8MHz, 4MHz, 2MHz, and 1MHz clock signals for using in a few of the logic modules.

My assumption is that since 48MHz, 24MHz and 12MHz are generated from the same PLL and are having a constant phase relationship, I can consider them as part of a single clock domain. And I can use a common reset signal synchronized w.r.t. 48MHz for resetting the flip-flops clocked by 48MHz, 24MHz or 12MHz. Is the above assumption correct?

For the generation of 8MHz, 4MHz, 2MHz and 1MHz clock signals I am using free running counters clocked at 48MHz (I could have used 24MHz also for this purpose, but 12MHz required fractional division to generate 8MHz out of it). I am confused whether the generated clocks 8, 4, 2, and 1MHz can be considered to be in the same clock domain as 48MHz. What should be the general rule in differentiating various clock domains?

Can I use the above mentioned reset signal for resetting the flip-flops clocked using 8, 4, 2, and 1MHz? Or should I generate separate reset signals for this purpose?


1 Answer 1


First part of the answer: Clocks coming from the same oscillator and produced in an internal PLL have a known phase relation. The tools know this and do check that transfers from one of these clocks to another do not end in a timing violation. Make sure that you have all appropriate constraints in the design and check output of the timing reports.

Second part of the answer: Don't do it this way. The best way is to use a single clock - 48 MHz in your case. All other clock domains can be replaced by your 48 MHz clock and a clock enable signal. For example, the 12 MHz domain is using a clock enable signal that is high in every fourth 48 MHz clock cycle. This saves a lot of trouble with clock domain crossings and even saves resources.

  • \$\begingroup\$ Thank you. To clarify myself, I should generate one clock using the PLL (48MHz in my case) and generate clock enable signals for all other clocks in the design viz. 24, 12, 8, 4, 2, and 1MHz. And I can use a common reset signal for resetting all the flip-flops in the design. Is this correct? \$\endgroup\$
    – rvkrysh
    Aug 2, 2016 at 2:20
  • \$\begingroup\$ @rvkrish Exactly. \$\endgroup\$
    – asdfex
    Aug 2, 2016 at 18:09

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