I am finding it confusing in defining various clock domains in the design. I did search over the Internet but I didn’t get a complete clarity on this.
In a certain FPGA (Actel ProASIC series) based design, I am generating three clocks – 48MHz, 24MHz, and 12MHz from an 8MHz crystal input using a PLL. Further, using one of these 3 clocks (48/24/12) I have to generate 8MHz, 4MHz, 2MHz, and 1MHz clock signals for using in a few of the logic modules.
My assumption is that since 48MHz, 24MHz and 12MHz are generated from the same PLL and are having a constant phase relationship, I can consider them as part of a single clock domain. And I can use a common reset signal synchronized w.r.t. 48MHz for resetting the flip-flops clocked by 48MHz, 24MHz or 12MHz. Is the above assumption correct?
For the generation of 8MHz, 4MHz, 2MHz and 1MHz clock signals I am using free running counters clocked at 48MHz (I could have used 24MHz also for this purpose, but 12MHz required fractional division to generate 8MHz out of it). I am confused whether the generated clocks 8, 4, 2, and 1MHz can be considered to be in the same clock domain as 48MHz. What should be the general rule in differentiating various clock domains?
Can I use the above mentioned reset signal for resetting the flip-flops clocked using 8, 4, 2, and 1MHz? Or should I generate separate reset signals for this purpose?