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I've designed an adder and the related testbench. I've run the RTL simulation, and it works as I expect, however I can't run the gate level simulation.

adder.vhd

library ieee;
use ieee.std_logic_1164.all;

entity adder is
port(x : in std_logic_vector(3 downto 0);
     y : in std_logic_vector(3 downto 0);
     z : out std_logic_vector(4 downto 0));
end entity adder;

architecture rtl of adder is
    signal c : std_logic_vector(3 downto 0);
begin
    adder_gen : for i in 0 to 4 generate
        half_adder_gen : if i = 0 generate
            z(i) <= x(i) xor y(i);
         c(i) <= (x(i) and y(i));
   end generate half_adder_gen;
        full_adder_gen : if 0 < i and i < 4 generate
            z(i) <= x(i) xor y(i) xor c(i-1);
         c(i) <= (x(i) and y(i)) or ((x(i) or y(i)) and c(i-1));
        end generate full_adder_gen;
        overflow_gen : if i = 4 generate
            z(i) <= c(i-1);
        end generate overflow_gen;
    end generate; 
end architecture rtl;

adder_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity adder_tb is
end entity adder_tb;

architecture tb of adder_tb is
    signal clk : std_logic;
    constant period : integer := 10;

    component adder is
    port(x : in std_logic_vector(3 downto 0);
           y : in std_logic_vector(3 downto 0);
         z : out std_logic_vector(4 downto 0));
    end component adder;    

    signal x, y : std_logic_vector(3 downto 0);
    signal z : std_logic_vector(4 downto 0);

begin

    adder_comp : adder
        port map(x => x, y => y, z => z);

    clk_process : process
    begin
        clk <= '0';
        wait for 5 ns;
        clk <= '1';
        wait for 5 ns;
    end process;

    inputs_submitt : process(clk)
        variable counter : integer := 0;
    begin
        if(clk'event and clk = '1') then
            if(counter mod 2 = 0) then
                x <= X"A";
               y <= X"B";
            else
                x <= X"5";
               y <= X"6";
            end if;
        end if;
    end process;

end architecture tb;

From the menu I do "processing -> start -> analysis and synthesis", it compiles fine. Then I do tool -> run simulation tool -> gate level simulation", after this ModelSim is being opened and what I get is the following error:

vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /adder_inst=adder_vhd.sdo -L altera -L altera_lnsim -L cyclonev -L gate_work -L work -voptargs="+acc"  adder_tb
# ** Error (suppressible): (vsim-SDF-3196) Failed to find SDF file "adder_vhd.sdo".
# 
# vsim -t 1ps "+transport_int_delays" "+transport_path_delays" -sdftyp /adder_inst=adder_vhd.sdo -L altera -L altera_lnsim -L cyclonev -L gate_work -L work -voptargs=""+acc"" adder_tb 
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./adder_run_msim_gate_vhdl.do PAUSED at line 12

Any suggestions?

Update: When I run analysis and synthesis the following is the output:

Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:10:21 2016
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:10:21 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file adder.vhd
    Info (12022): Found design unit 1: adder-rtl
    Info (12023): Found entity 1: adder
    Info (12022): Found design unit 1: adder-rtl
    Info (12023): Found entity 1: adder
Info (12021): Found 2 design units, including 1 entities, in source file adder_tb.vhd
    Info (12022): Found design unit 1: adder_tb-tb
    Info (12023): Found entity 1: adder_tb
    Info (12022): Found design unit 1: adder_tb-tb
    Info (12023): Found entity 1: adder_tb
Info (12127): Elaborating entity "adder" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 8 input pins
    Info (21059): Implemented 5 output pins
    Info (21061): Implemented 6 logic cells
    Info (21058): Implemented 8 input pins
    Info (21059): Implemented 5 output pins
    Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 908 megabytes
    Info: Processing ended: Tue Aug 02 14:10:31 2016
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:23
    Info: Peak virtual memory: 908 megabytes
    Info: Processing ended: Tue Aug 02 14:10:31 2016
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:23
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:10:32 2016
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:10:32 2016
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder
Info: qfit2_default_script.tcl version: #1
Info: Project  = adder
Info: Revision = adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device 5CGXFC7C7F23C8 for design "adder"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
    Extra Info (176219): No registers were packed into other blocks
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
Critical Warning (332012): Synopsys Design Constraints File file not found: 'adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45
    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.12 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
Info (144001): Generated suppressed messages file C:/altera_lite/16.0/adder/output_files/adder.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 2666 megabytes
    Info: Processing ended: Tue Aug 02 14:11:01 2016
    Info: Elapsed time: 00:00:29
    Info: Total CPU time (on all processors): 00:00:55
    Info: Peak virtual memory: 2666 megabytes
    Info: Processing ended: Tue Aug 02 14:11:01 2016
    Info: Elapsed time: 00:00:29
    Info: Total CPU time (on all processors): 00:00:55
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:02 2016
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:02 2016
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 879 megabytes
    Info: Processing ended: Tue Aug 02 14:11:08 2016
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:07
    Info: Peak virtual memory: 879 megabytes
    Info: Processing ended: Tue Aug 02 14:11:08 2016
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:07
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:09 2016
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:09 2016
Info: Command: quartus_sta adder -c adder
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1100mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 1240 megabytes
    Info: Processing ended: Tue Aug 02 14:11:15 2016
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:05
    Info: Peak virtual memory: 1240 megabytes
    Info: Processing ended: Tue Aug 02 14:11:15 2016
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:05
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:16 2016
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 14:11:16 2016
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off adder -c adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
Info (204019): Generated file adder.vho in folder "C:/altera_lite/16.0/adder/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 796 megabytes
    Info: Processing ended: Tue Aug 02 14:11:17 2016
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
    Info: Peak virtual memory: 796 megabytes
    Info: Processing ended: Tue Aug 02 14:11:17 2016
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 16 warnings

Update 2: Following suggestions...

If I do only Analysis and Synthesis I get the following:

Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
    Info: Processing started: Tue Aug 02 16:59:56 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file adder.vhd
    Info (12022): Found design unit 1: adder-rtl
    Info (12023): Found entity 1: adder
Info (12021): Found 2 design units, including 1 entities, in source file adder_tb.vhd
    Info (12022): Found design unit 1: adder_tb-tb
    Info (12023): Found entity 1: adder_tb
Info (12127): Elaborating entity "adder" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 8 input pins
    Info (21059): Implemented 5 output pins
    Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 908 megabytes
    Info: Processing ended: Tue Aug 02 17:00:07 2016
    Info: Elapsed time: 00:00:11
    Info: Total CPU time (on all processors): 00:00:24

(No .sdo file in this case).

If I do the place and route instead:

Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off adder -c adder
Info: qfit2_default_script.tcl version: #1
Info: Project  = adder
Info: Revision = adder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device 5CGXFC7C7F23C8 for design "adder"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08
Critical Warning (332012): Synopsys Design Constraints File file not found: 'adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y35 to location X89_Y45
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
Info (144001): Generated suppressed messages file C:/altera_lite/16.0/adder/output_files/adder.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 2670 megabytes
    Info: Processing ended: Tue Aug 02 17:02:05 2016
    Info: Elapsed time: 00:00:30
    Info: Total CPU time (on all processors): 00:00:54

No .sdo file in such case either...

\$\endgroup\$
  • 1
    \$\begingroup\$ Your .sdo file is missing. Did you run through all the steps i.e. Analysis, fitting etc.? \$\endgroup\$ – user110971 Aug 2 '16 at 13:01
  • \$\begingroup\$ I did what I said xD. What are supposed to be such steps? It's possible I've skipped some of them. I mean when I do "analysis and synthesis" it runs analysis, fitter, assembler timequest timing EDA netlist writer, each of these are fine. \$\endgroup\$ – user8469759 Aug 2 '16 at 13:02
  • \$\begingroup\$ They are on the bottom left in Quartus. See here: web.eecs.umich.edu/~pmchen/engr100/lab1/compile2.png \$\endgroup\$ – user110971 Aug 2 '16 at 13:05
  • \$\begingroup\$ Ok, then they run fine. Can I check somehow if any of such steps spits out the file you mentioned earlier? \$\endgroup\$ – user8469759 Aug 2 '16 at 13:06
  • \$\begingroup\$ Should be in the messages. You can search for it in your directory. \$\endgroup\$ – user110971 Aug 2 '16 at 13:08

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