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The 18 serial streams are not encoded or scrambled. The idea is to multiplex them onto one or more encoded serial streams at higher rates for onwards transmission over optical fiber.

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  • \$\begingroup\$ ASIC for lossless compression, encapsulation into ethernet and transmission over 10GbE? \$\endgroup\$ – RJR Aug 3 '16 at 8:22
  • \$\begingroup\$ @RJR Thx. ASIC would be too expensive for the application. \$\endgroup\$ – shparekh Aug 3 '16 at 8:24
  • \$\begingroup\$ FPGA, then. It's the only way you can process that much. \$\endgroup\$ – pjc50 Aug 3 '16 at 8:26
  • \$\begingroup\$ To stand any chance the individual data lines need to be synchronized also. \$\endgroup\$ – Andy aka Aug 3 '16 at 9:11
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You could use a MAX3952 for serializing up to 16 inputs into a 10 Gbps stream. For 18 inputs you have to use 2 devices: -

enter image description here

The equivalent deserializer is the MAX3950.

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  • \$\begingroup\$ Thx. This part is no longer available. But upvoted for the concept. I wonder how they handle the framing signal associated with the ADC outputs. \$\endgroup\$ – shparekh Aug 3 '16 at 17:10
  • \$\begingroup\$ @shparekh shame it's no longer available. Framing might be done like their slower part MAX9205 - they insert a hard start bit at the beginning and a hard stop bit at the end after all 16 have been serialized. The receiver takes some micro seconds to lock on AND you need to have scrambled data on each input to prevent long-term mis-lock. \$\endgroup\$ – Andy aka Aug 3 '16 at 17:38
  • \$\begingroup\$ Looks like TI's DS32EL0421/DS32EL0124 is a similar part and quite suitable. If this part works out, then I do not need any complexity that comes with FPGAs or ASICs to transport the data from ADCs to the processor boards. @Andy, marking your answer as accepted. Devices come and go concept remains the same. Please share if you have any insights about this part. \$\endgroup\$ – shparekh Aug 4 '16 at 22:24
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Presuming you really do mean 600 Mbps and not 600 Msps times some number of bits, 18 x 600 Mbps = 10.8 Gbps. 10G Ethernet is 10 Gbps, so it would probably be doable without any compression if you run the serdes blocks a little faster. You could probably get away with a Kintex 7 FPGA to do the multiplexing and demultiplexing. What is the interface to the ADCs?

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  • \$\begingroup\$ Interesting thought on running the serdes a little faster. I found a SerDes based solution to interface with the ADCs. Please see my answer. \$\endgroup\$ – shparekh Aug 4 '16 at 22:19
  • \$\begingroup\$ Well, a little faster as in faster than the Ethernet spec, but within the FPGA serializer specs. With those TI chips, you'll still need at least 4 parallel links. And you may still need an FPGA to get things interfaced properly. Hard to say for sure though, as I have no idea what interface your ADCs have. \$\endgroup\$ – alex.forencich Aug 4 '16 at 22:49
  • \$\begingroup\$ Yes! Indeed there is an fpga at the other end. But the problem is I can't keep it close to the adcs. Hence... \$\endgroup\$ – shparekh Aug 6 '16 at 6:10
  • \$\begingroup\$ My point is you may need an FPGA between the ADCs and the serializer as well. \$\endgroup\$ – alex.forencich Aug 6 '16 at 12:06
  • \$\begingroup\$ Adcs have a source synchronous lvds interface which is exactly the input that the TI devices take. Subsequently the devices serialize four lvds inputs and encode them for transmission on a balanced line. So on paper it all looks like I do not need an fpga to pass the data down from the adcs to the fpga at the end of the cable. \$\endgroup\$ – shparekh Aug 7 '16 at 14:35

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