I am fairly familiar with the concept of metastability: You have two asynchronous clock domains, there is no way to guarantee that the data will be setup/held properly when input to a flip flop if it's clocked from a different domain (especially with differing clock frequencies that are not integer multiples of one another). The state of the register output will react unpredictably.
In a slow moving single bit case: Typical design will just pipeline some "protection" registers in the new clock domain before utilizing the signal, giving the metastable state time to resolve.
On a fast moving/wide bus signal it is not as simple. The unpredictable nature of metastability may cause some bits of a bus to settle earlier than others (assuming you can't perfectly match all register input trace lengths and perfectly match the register timings), which can look like glitches. In this scenario, designers can utilize a clock crossing FIFO to reliable pass data back and forth.
So what do the guts of a clock crossing FIFO look like and how does it get around the fundamental issue of asynchronous timing?