# Can Lipo protection boards be daisy chained?

I've got several 1S Lipo protection boards. Would it be possible/safe to daisy chain them to make higher voltage packs? Example:

        Balance Charger Port 3     Balance Charger Port 2      Balance Charger Port 1
|                   |                   |
------Brd1----  |   -----Brd2-----  |   ----Brd3------  |   -----Brd4-----
P+  B+  B-  P-  |   P+  B+  B-  P-  |   P+  B+  B-  P-  |   P+  B+  B-  P-
+14.1V --┙   |    |  └---┴---┙    |    |  └---┴---┙   |    |  └---┴---┙   |    |  └---GND
+Battery-            +Battery-           +Battery-           +Battery-


Let's assume that the application would not require more current that any one of the protection boards can deliver.

EDIT: As requested below, here is a bit of info on the boards I've got in my drawer: product details Maximum charging current : 3A Maximum discharging current: 3A Charging cut-off voltage: 4.2V Discharging cut-off voltage: 2.75V Battery protection chip models: DW01 MOS model: 8025 Function: Overcharge, over discharge, short circuit protection

Datasheets: DWO1 8025 MOSFET

• I would assume that this is reasonable, but will let someone write a more authoritative answer. Also, welcome to EE.SE! – user2943160 Aug 5 '16 at 0:04
• Yes. you can do that, and it's very safe. – Atmega 328 Aug 5 '16 at 5:18
• The charge and discharge FET's would have to be rated for the full stack voltage. Often they are 8V or 12V rated. Low resistance PTC's (which are sometimes included in protection circuits) also have low voltage ratings. – mkeith Aug 5 '16 at 5:38
• All protection boards these days use MOSFET. Not only they don't need to rated for the full stack, most MOSFETs designed for 3.6V Lipo protection board have 20+ Drain-Source Voltage. – Atmega 328 Aug 5 '16 at 6:46
• I have seen 8V and 12V FET's used. Why wouldn't the FET need to be rated for the full stack voltage? Let's say you have an 8s pack, and one protection circuit tries to turn off the discharge FET. What would be the Vds across the discharge FET when that happens? – mkeith Aug 5 '16 at 7:00

The protection circuit will not generally be designed for multiple cells. Keep in mind that in a series stack, the individual cell protection circuit will be exposed to the full stack voltage if it should ever try to open the circuit. Probably for 2S this will be OK. Maybe 3S. Beyond that, I think you will find that the charge and discharge FET's are not rated high enough for the applied voltage. If the protection circuit has a PTC, the PTC will also probably have a very low Voltage rating. Maybe lower than the FET's.

Note that you would never know if it would work UNTIL the protection circuit opens. For normal use, it would work fine (as would unprotected cells). You can probably find a million people who have done it with no problem because the protection circuit never opened on them.

But why pay for a circuit that will fail if it ever operates? That is like buying an insurance policy that will never pay off.

Since there is so much chatter about this I am going to add a few more things to my answer. Look at the circuit below, which represents a short circuited 3S battery pack. The FET's in series with each cell are the discharge FET's that are part of a typical protection circuit. I have not shown the charge FET's, as they don't really matter in this scenario. I drew the gates unconnected, but they would be connected to the battery protection IC which is also not shown. it would control the gate.

simulate this circuit – Schematic created using CircuitLab

In short circuit conditions, the battery protection IC is going to turn off the discharge FET. This will not happen simultaneously for every protection circuit. Whichever one opens first will then feel the full battery pack voltage. Hopefully that is now clear since I added the schematic.

Once you see that, hopefully you will also see that it doesn't matter whether the load is 0 Ohms (impossible) or 0.1 or 1 Ohm. Once the current drops to zero, the voltage across the load will also drop to zero, and the open FET will feel the full battery pack voltage from drain to source.

There is one more thing worth noting. The protection IC in a typical protection circuit may also fail if the FET fails. It will typically have a lower VDD max than the discharge FET.

Also, the same scenario happens during charging UNLESS it is a multi-cell charger with bypass. If the battery pack is over-charged with a two-terminal charger, and one of the charge FET's tries to open, it will feel the full charger voltage across its drain to source.

Hopefully it is now clear why it is not a good idea to stack batteries with individual protection circuits UNLESS you have detailed specifications for the circuits.

• During discharge, if any of the protection boards open the circuit (let's say at low voltage cutoff), the remainder of the circuit would be subjected to zero voltage (open circuit) wouldn't it? During charging, I'm not certain what mode they go into to prevent over volting, but aren't balance chargers designed for detecting voltage imbalances and then compensating (if possible) or shutting off the charger if it can't compensate? – user49831 Aug 6 '16 at 2:23
• The protection circuits can open during charge due to over-voltage or over-current. During discharge they can open due to under-voltage or over-current. During charge, the individual cell will not experience high voltage. You are right about that. But if it opens due to over-current during discharge into a load, there is a good chance the protection circuit will fail (if the series voltage is greater than max voltage of protection circuit mosfets). – mkeith Aug 6 '16 at 3:17
• Are you saying protection circuits have a mode where they short rather than open? Why would they, as that sounds rather dangerous? If they open (rather than short) then the entire circuit stops, because thats how series circuits work. OTOH, if they short, or produce transitional spikes, that could be problematic. – user49831 Aug 6 '16 at 19:04
• @user49831, no I am not saying protection circuits have a mode where they short rather than open. What I am saying is that the ability of a FET to maintain an open circuit depends on the voltage applied between drain and source. If the voltage is large enough, the FET will fail or go into avalanche, and in either case there will be conduction from drain to source, even if the gate to source voltage is zero. This is why the FET Vds max rating must be greater than the combined cell voltage. – mkeith Aug 6 '16 at 20:36
• The FET I am talking about is part of a typical protection circuit. Vds rating would probably be 8, 12 or 20 V. Any of those is fine for a single cell, but 12V might fail in a 3s stack, and 20V might fail in 5s. – mkeith Aug 6 '16 at 20:38