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I know that the "third state" of a tristate buffer is a high - impedance output. But my question is what about the input impedance? Will it also change to high - Z?
Whatever article I read about a tristate buffer, no one seems to talk about the input impedance, so my second question is that does it even matter if the input impedance is low or extremely high?
On regular, CMOS digital chips, the impedance of an input is always high.
By definition, the internal implementation of an input should not influence the level of that input. Only the external components should be able to decide on whether the input is high or low. Otherwise, it becomes an output.
It is as simple as that.
And actually, an output that is high impedance is often exactly configured in the same way as an input, on a MCU. It has exactly the same behavior.
To be more explicit, here is how a general-purpose input/output (GPIO) pin is implemented within an MCU:
There are only three valid states: OutputH on and OutputL off (the pin is a high-level output), OutputH off and OutputL on (the pin is a low-level output), or both OutputH and OutputL off (the pin is either an high impedance output or an input). The difference between a high impedance output and an input is simply whether the Input value is used or unused from the firmware. As an aside, the state where both OutputH and OutputL are on is invalid, as this would create a short between Vcc and GND.
Note that I took the example of MCU GPIO pins here, because they can be configured in any state you want, but the principle is the same for any kind of digital chips (logic chips, etc): an input is always high-impedance.
I feel like these answers are overly complex for the question.
A typical CMOS tri-state inverter is shown below. You can see that the input capacitance is just gate capacitance plus any parasitics, regardless of the value of OE. MOSFET gates are capacitive. They may draw a very small leakage current but this is in most cases negligible.
When OE is activated, both the series NMOS and PMOS switch on and allow for the input to cause a toggle at the output.
When the OE is inactive, the supply voltage and ground are cut off from the output. This high-z state can be measured on the order of MOhms.
If you're using a BJT tri-state then the input impedance will drop by quite a lot in most cases (since BJT's are current controlled devices). But, when someone says tri-state buffer they typically mean CMOS, in my experience.
A tristate buffer isn't complicated. Ideally, it looks about like this:
simulate this circuit – Schematic created using CircuitLab
(I've included BUF1 and BUF2 mostly to illustrate that the input impedance can be different from the output impedance that is coupled to/through SW1. But you can also just mentally ignore them for some thinking purposes, if that helps you.)
Where SW1 is controlled by BUF2 (with some unknown input impedance.) Note that when SW1 is in position TRI, that the output floats. That's also known as high impedance because it isn't connected to anything. (In practice, nothing is so perfect as that, so there will be some very small conductance present.) When SW1 is in the ~TRI position, then the output will have the conditions of BUF1's output (impedance, voltage source, etc.)
In logic, of course, the input will be allowed to be whatever signalling is used for a "0" or a "1" and most practical designs will have BUF1's input impedance as high as possible so as to reduce the loading on whatever is driving it. (Similarly, BUF2's input impedance will also be as high as practical.)
There is also something related called an open-collector or open-drain output. These look more like the following case:
Note that in this case the logic value at the input controls SW1. (In the first case above (the first schematic), the input logic value doesn't control SW1.) The output will either be a low impedance output "0" or else a high impedance "1". These are also useful to know about. You can see their output as either "0" or "tristate."
The tristating control input impedance should be as high as practical. But even that is a matter of circumstances. I suppose if one is trying to drive it with a 50 ohm coax/driver situation, you might prefer that input to have a matching impedance. (Don't know of any situation where that happens, though.) The input itself (first circuit case) normally also has as high an impedance as possible where logic states are involved. Though if the input were to be an analog signal of some kind then it might be best to completely remove BUF1 somehow and actually just have a wire to pass along that analog signal as accurately as possible.
I think the implied question originally was whether going to the high impedance state on output also puts the input into a high impedance state.
Going to the high impedance state only puts the output into high impedance. The input impedance does not change. If you want to unload the input from the source of the signal, perhaps in there are so many devices on a bus that you want to disconnect devices that are in a high impedance state, you would want to add a high impedance buffer before the input to the tristate stage. Of course, the point is moot if the device has a high impedance to begin with.
