Assuming I wan't to implement a state machine in verilog, where I have 1 output which is a register So the output must be in sync with the input clock. I know that the transitions between the machine states should be implemented via sequential block, for example:
always @ (posedge clock) if (state) state <= 1'b0; else state <= 1'b1;
If I want the output to be in sync with the clock, will implementing the output result via combinatorial will do? I mean:
always @ (state) if (state) Out_Reg = a; else Out_Reg = b;
Does this implementation still valid for Out_Reg to be a positive edge triggered register?
Or should I make assignment to Out_Reg in the sequential block for it to be a valid synced output register?