# How to handle Register output in state machine with verilog

Assuming I wan't to implement a state machine in verilog, where I have 1 output which is a register So the output must be in sync with the input clock. I know that the transitions between the machine states should be implemented via sequential block, for example:

always @ (posedge clock)
if (state)
state <= 1'b0;
else
state <= 1'b1;


If I want the output to be in sync with the clock, will implementing the output result via combinatorial will do? I mean:

always @ (state)
if (state)
Out_Reg = a;
else
Out_Reg = b;


Does this implementation still valid for Out_Reg to be a positive edge triggered register?

Or should I make assignment to Out_Reg in the sequential block for it to be a valid synced output register?

You should probably synthesize your design to be sure, but I expect that your example will result in Out_Reg being generated from combinatorial logic. It could more conventionally be expressed as

wire Out_Reg;
// ...
assign Out_Reg = state ? a : b;


If you want Out_Reg to be the output of a physical register (flip-flop), you could write

reg Out_Reg;
// ....
always @(posedge clock) begin
Out_Reg <= state ? a : b;
end


But then, of course, the value of Out_Reg is delayed by one clock cycle relative to the state of state. If you need it to be in sync, you would need to duplicate the state logic so that Out_Reg anticipates what the next state of state will be. You could simplify this by using combinatorial logic to create a next_state signal:

wire next_state;
reg state, Out_Reg;

assign next_state = /* logic to determine next value of state */
always @(posedge clock)
state <= next_state
// ...
always @(posedge clock)
Out_Reg = next_state ? a : b;


However, you should also consider whether this is necessary. Does your downstream logic really care whether the output of this module is physically sourced from a register or from a combinatorial gate?