I'm trying to design a purely resistive load that is digitally controlled. The idea is of an array of resistors that are driven with power MOSFET's. I want to feed a current pattern into the microcontroller and for the load array to follow it.

the following image gives an idea of what I'm trying to do: LoadStep

It is a resistive array to provide different levels of current load. Every Resistor is switched on and OFF with a power MOSFET. The whole is going to be used to test a voltage regulator. The applied Voltage is 5V and the current is up to 1 A.

To obtain a specific Current Value the corresponding Resistors has to be switched on.

As an Example to get a current of 600 mA , the resistances delivering 100 mA (R= 50Ohm) and 500 mA (R= 10Ohm) will be on, the rest will be off. I'm planning 16 resistors. The switching between load steps has to be smooth and occur under 2µs. My concern is the transition process between two load steps.

Example : switch between step1 (R1= ON,R4=ON, rest OFF) and step 2 (R3=ON, R10=ON, R11=ON, rest OFF)

The state of the corresponding switching transistors is saved in a register and will be latched simultanaeously for all transistors. I'm using IRLML0040TRPbF (Datasheet)

The controlling microcontroller is an XMC1100.

I don't want to programm intermediary steps for the transition to be able to hold the timing criteria of 2µs.

I thought, as I don't have an inductive load, I don't need extra circuitry to assure the smootheness of the current step transistion.

am I right in that line of thought? will the current flowing in the resistors during the transition disturb the smootheness of the transistion significantly, even if I latch (from the µcontroller) simultaneously and the transistor is quite fast?

Do you guys have an idea how to proceed in that case?

I'm quite the beginner and would be grateful for any help.

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    \$\begingroup\$ You will get much better answers if we don't have to guess. Explain what you are really trying to do. Provide a schematic of the basic layout. (You can use the schematic button on the editor toolbar.) What is the voltage, current, power, etc.? Is the load connected to ground, positive supply or neither? Put all the details in your question and not in the comments. Welcome to EE.SE. \$\endgroup\$
    – Transistor
    Aug 7, 2016 at 20:39
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    \$\begingroup\$ This is one of those time where explaining the overall idea might be in order. We have no idea what kind of current you expect to pull. If it is really small, then why not use a digital pot? Like in the volume control of many stereos. \$\endgroup\$
    – st2000
    Aug 7, 2016 at 20:41
  • \$\begingroup\$ thank you , I edited the question to get a clearer idea. \$\endgroup\$ Aug 7, 2016 at 21:12
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    \$\begingroup\$ I think it will work. I couldn't read your schematic details, but I would start with 0 Ohms in series with each gate unless that causes problems. It is good to have a series resistor and gate pulldown resistor in the schematic in case they are needed. But I would start with series = 0 and pulldown not installed. If you have a choice, set the drive strength on the gate IO pins to max. \$\endgroup\$
    – user57037
    Aug 7, 2016 at 21:37
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    \$\begingroup\$ If the regulator responds poorly to load step, you may be able to fix it with additional output capacitance on the regulator. But usually if you follow the regulator guidelines for schematic and layout, the step response will be small and recover quickly. \$\endgroup\$
    – user57037
    Aug 7, 2016 at 21:39

2 Answers 2


You've built an DAC! Congratulations :)

Usually, you'd build something like an "2R-Ladder DAC", to allow for a linear range of resistances to be built.

I don't want to programm intermediary steps for the transition to be able to hold the timing criteria of 2µs.

That would be equivalent of a 500 kHz bandwidth, ie. a 1 MS/s sampling rate. That should work if you can program your microcontroller to change things at that rate.

However, it'll probably be much easier to do something else:

  1. use a voltage DAC that fulfills your bandwidth requirements
  2. feed the output voltage to the non-inverting input of an opamp
  3. feed the output of the opamp to the gate of a field-effect transistor rated to carry your current.
  4. simulate a resistive load by connecting your power source across the FET; put a small fixed resistor in series with that.
  5. use the voltage drop across that resistor (proportional to current flowing through the FET!) together with a voltage divider to your DAC's output to drive the non-inverting input of your opamp; you might need some biasing, depending on your individual components.

Look for "transconductance amplifiers based on FET" if you want to see more of this Voltage-to-Current converter scheme (A resistor is a device that lets through a voltage proportional to current). The trick is to use a voltage divider to simulate a linear dependency between input voltage and current; it's only valid for a certain range of voltages.


First things first. As it stands, the circuit will not work, since the gate drive is not referenced to the FET sources. You need to connect V_CONTROL (pin 1 on your 16 drive connectors) to GND.

With that done, you should be in pretty good shape. Your gate drive resistors are only 1k, and the FET Ciss is only about 270 pF, so the time constant is about 1/4 microsecond, which is comfortably below your desired settling time of 2 usec. However, the transition will NOT be smooth on the time scale of 10s of nsec. Specifically, the FETS which are active and get turned off will not do so at exactly the same time as the others which were off and get turned on. Everything should settle out well before your 2 usec time limit. As Marcus Muller has pointed out, what you've created is a form of DAC, and for real DACs, glitches due to bit skew is a fact of life.

Consider 2 FETs, one off and the other on. Assume the threshold voltage for each FET is 1.8 volts, and the gate drive voltage swings between 0 and 5 volts. Simultaneous transitions of the gate drives will activate the OFF FET after about 1/2 time constant, or 130 nsec, while the ON FET will not turn off until about 1 time constant, or 260 nsec. From 130 to 260 nsec both FETs will be off. A second-order complication arises from the fact that different FETs will have slightly different threshold voltages, so their delays will be slightly different, although this will be a very small effect.

Finally, with the very fast switching times of your FETs, you may well get ringing on your load when you change currents due to the relatively long leads from the power supply to the load.

So, what does "smooth" mean?


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