A little background: I'm trying to extract a gate signal from someone else's circuit (ckt1) so that I can synchronize events in my design (ckt2) to a sequential trigger in theirs. First problem is I have no way of accessing a schematic or firmware for their design, so I'm having to get creative. What I do have is ckt1's status LED's which light up during the gate events I'm interested in extracting. The LED's (and current limiting resistors) are arranged in a 4x4 matrix controlled by darlington transistor pairs (best I can tell anyways). These are the nodes I'm breaking out to ckt2 (left of the black line in picture). Second problem is the LED's aren't held high for the duration of the gate on signals of interest, rather they are driven by PWM (presumably to save battery and soften the light). So The circuit on the right half is what I've devised to reproduce the longer gate signal from the PWM.
In their off state, the LED/CLR pairs are floating between two transistors (at least one transistor in off state anyways). As a result, their common mode voltage when off is relatively low, but their voltage WRT ground is all over the place. So my first question is, can I get away with having these inputs to ckt2 floating? (ie. no common ground connection between the the two circuits). In my first tests, no common ground produces a cleaner output when viewed on the oscope. But are there any potential long term problems? The only one I foresee is that elsewhere in the circuit I'm extracting some signals which are referenced to ckt1 GND, so I'm thinking I'll have to use a rail splitter to create a virtual GND in ckt2 to connect to this reference (thus preserving the floating inputs in the circuit above).
Also, I realized I could eliminate one schmitt inverter on the output if I instead reference the subtractor to +12, swap the inputs, and change the subtractor/inverter interface as shown below. Is there anything wrong with referencing the subtractor to the positive rail like this?