I came across an issue at my workplace with the following circuit. I did a OL response and saw that the gain margin is 21 db and the phase margin is 14 deg. Clearly not so good. Note that the 680nF cap is a populated capacitor on a board!!

enter image description here

I measured the test point (TP) with a scope and saw a small oscillation of 50mV @ 42khz. I thought this was interesting because the last few times I saw an unstable circuit they oscillated rail to rail. The oscillation I'm seeing doesn't appear to be from instability - I think it is from a power up charge on the cap and the feedback of the amp is trying to drive it to the correct voltage, causing a small oscillation when it overshoots. When the network is disturbed (a colleague touches the 1.3k resistor lead) it stops oscillating. A power cycle will sometimes cause it to oscillate again. Anyone have a better explanation or reading material I can bush up on?

My inclination is to depopulate the cap from the BOM. But I would like to try to understand the original designer's intent. I tried searching online for circumstances why you would try to put extra capacitance on an output of an op-amp circuit. I find a lot of information about remedies and negation techniques. Does anyone have any interesting stories or reasons where they added a load cap to an op-amp output?

UPDATE enter image description here On power up this is kicked into an oscillation that settles around 400 mV pk-pk. Clearly acts unstable-no surprise with the given phase margin. I'm just not clear on the mechanics that dictate how it settles at 400 mV.

  • \$\begingroup\$ Just out of curiosity, have you probed with the oscilloscope the op amp's power pins to check for voltage oscillations on the power rails? In other words, are you sure you don't have an unstable LDO voltage regulator, for example? \$\endgroup\$ – Jim Fischer Aug 9 '16 at 16:05
  • \$\begingroup\$ Yes, getting a small ripple from the rails, but well hidden in the measurement noise. \$\endgroup\$ – klamb Aug 9 '16 at 17:53
  • \$\begingroup\$ @klamb - don't neglect to accept one of the answers. That's how your respondents are "paid" for their work :) \$\endgroup\$ – scanny Aug 20 '16 at 6:03

The designer might have intended to make a band pass or low pass filter, but neglected to put any impedance/resistance between the capacitor and the op amp. But this is purely speculation and EE.SE has no place for that.

One thing to remember is amplifiers and ADC's have input impedance, in this case R1 is 30kΩ (from the datasheet) enter image description here

I can't see a reason to keep the capacitor on the board in its current configuration it's loading the op-amp with capacitance, either convert the circuit into a low pass filter (and cut back on your noise) A good reference is Op Amps for Everyone from TI or any op amp design guide from an analog manufacturer.

Learn how to do filter calculations, check the LT1001 datasheet for info on capacitance (fig 1001 G20) for info on overshoot. Design stuff with hand calculations, then maybe do a simulation in LT spice and then implement the changes and test them to see if they improve your situation.

  • \$\begingroup\$ I agree the 680 nF cap makes no sense. If they wanted to roll off the gain. (LP) then much better to put a cap in parallel with the 10 k ohm resistor in the feed back path. (Oh circuits don't always oscillate to the rails.) \$\endgroup\$ – George Herold Aug 9 '16 at 15:57
  • \$\begingroup\$ Because by putting the 680nF cap combined with the output impedance of the amplifier, it introduces a "hump" in the transfer function at higher frequencies. cds.linear.com/docs/en/application-note/an148fa.pdf In short, you are causing instability. Also, If you look at graph 1001 G20, and think of it like an under damped system when you increase the overshoot. If you keep increasing the capacitance in the system, eventually the system will never dampen out and oscillate. \$\endgroup\$ – Voltage Spike Aug 9 '16 at 17:21
  • \$\begingroup\$ Note there is already a pole created from the RC prior to the op amp stage. From a system standpoint - there is no need for a bandpass in this application. It seems like intentionally adding load capacitance to the output of an op amp is pretty far fetched - hence why I am interested in the intent.. \$\endgroup\$ – klamb Aug 9 '16 at 19:00
  • \$\begingroup\$ As far as the intent goes, I think the intent was to cut back on noise or create filtering, like you would on a power rail without considering the problems it would cause. You can't just salt and pepper caps in an analog signal chain, you can get away with it on power rails because they mostly operate at DC. \$\endgroup\$ – Voltage Spike Aug 9 '16 at 19:04
  • \$\begingroup\$ Yeah that's where our heads landed too. Although, I like Spehro's thought. But this is a slow input signal before the 33hz filter.. and that's a lot of cap on the output. \$\endgroup\$ – klamb Aug 9 '16 at 19:12

The op-amp output does not necessarily behave in a linear manner- there will be current limiting and slew rate limiting for example. So it's not unusual for this kind of mistake to show up as small amplitude oscillations.

Sometimes a small amount of capacitance on the output or across inputs is helpful in extreme EMI situations, but at the expense of stability and noise.

Try to determine the phase margin with a smaller amplitude signal- it clearly is close to zero.


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