The DAC requires a clock pulse (I'm sending in a 50MHz one, which I've divided from the FPGAs 100MHz clk), which I'm sending in through pin 4, following the reference manual. However, once I try to synthesize and implement it, I get an error.
"Poor placement for routing between an IO pin and BUFG. If this sub-optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .XDC file to demote this message to a warning. However, the use of this override is highly discouraged. These examples can be used directly in the .XDC file to override this clock rule. "
There are two possible problems:
The fpga doesn't like that I'm outputting a clock signal through this PMOD pin
There may be an issue with Mset_enable, but it has nothing to do with a clock (right now it's an input assigned to one of the on-board buttons), and I see no reason why there should be difficulty placing it.
My question is: which problem is it, and should I go ahead and use this workaround?
module tuning_word_set( input [3:0]data_in, input clk, input Mset_enable, output reg sin_LUT_rst, output reg [3:0]data_out ); //if enabled, M will change to data_in, otherwise it will stay the same always @* begin if (Mset_enable) begin data_out <= data_in; sin_LUT_rst <= 1'b1; end else data_out <= data_out; sin_LUT_rst <= 1'b0; end endmodule