Sending a divided clock through a non-dedicated clock pin?

Question

I'm moderately new to FPGA's, and right now I'm working on code to interface with a DAC. I'm using this PMOD DAC , and a Nexys 4 DDR fpga. Right now, I'm connecting them through the JB PMOD header.

The DAC requires a clock pulse (I'm sending in a 50MHz one, which I've divided from the FPGAs 100MHz clk), which I'm sending in through pin 4, following the reference manual. However, once I try to synthesize and implement it, I get an error.

"Poor placement for routing between an IO pin and BUFG. If this sub-optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .XDC file to demote this message to a warning. However, the use of this override is highly discouraged. These examples can be used directly in the .XDC file to override this clock rule. "

There are two possible problems:

1. The fpga doesn't like that I'm outputting a clock signal through this PMOD pin

2. There may be an issue with Mset_enable, but it has nothing to do with a clock (right now it's an input assigned to one of the on-board buttons), and I see no reason why there should be difficulty placing it.

My question is: which problem is it, and should I go ahead and use this workaround?

Mset code:

module tuning_word_set(
  input [3:0]data_in,
  input clk,
  input Mset_enable,
  output reg sin_LUT_rst,
  output reg [3:0]data_out
  );

//if enabled, M will change to data_in, otherwise it will stay the same
always @*
begin
  if (Mset_enable)
  begin
    data_out <= data_in;
    sin_LUT_rst <= 1'b1;
  end
  else
    data_out <= data_out;
    sin_LUT_rst <= 1'b0;
end

endmodule

Answer 1

What you can try, rather than dividing the clock, is just creating a 50 MHz clock in the constraints file, and tying that the output pin.

This will get you started on the right track: http://www.xilinx.com/support/answers/62488.html

Answer 2

Only some of the input pins are connected to the clock distribution networks inside the FPGA.

The clock routing is specialized because it supports a higher fanout, so large parts of the FPGA can use the same clock signal.

It is possible to use a regular routing interconnect as a clock, but this has so many interesting constraints on it that the compiler will generate a design that uses way too many resources, and will run slowly. When you add more logic, the compiler will generate a clock tree out of LUTs, which will reduce \$f_{max}\$ for your design, so expect it to fail timing constraints once you pick up some complexity. So the workaround will not take you very far.

So, neither of your ideas will work, the problem is on the input side, with the assignment of the clock signal to a specific input pin.