I’m trying to understand the way PRESET and CLEAR work on a positive edge triggered D flip flop, but I may be missing something that I hope someone can clarify please.
Figure1 below shows the flip flop in question. I am using red for high and blue for low. The positive edge detection device is an AND gate with a NOT gate. The output from the edge detector in this diagram is low so the flip flop cannot have its state changed by a change in D.
Figure2 below is a brief moment when the clock edge is rising. The output from the edge detector is high so Q changes to match D.
And Figure3 below is another moment when the clock edge is rising, so again Q samples D and changes to match.
As long as PRE and CLR are both high, the flip flop behaves exactly as I would expect. A three input NAND gates only outputs a 0 when all three of its inputs are high.
But here’s my query. In Figure4 below, the active low CLR input goes low, while there is a rising edge, so the flip flop is enabled. The inverse of Q is now high but Q is not set to 0 as I would expect. There is still a low input to the top right NAND gate, so Q is still high.
In Figure5 below the active low PRE input has been set to low. This is happening on the rising edge again, while D is low. It will make Q high as it should, but Q’s inverse is also high.
For the majority of the time there is no rising edge, and the PRE and CLEAR behave correctly, as in Figure6 and Figures7. I am concerned because a lot of literature (websites etc.) say that the PRE and CLR inputs are asynchronous and completely independent of the input at D, and of the clock. Can someone please clarify this for me?