# Positive Edge Triggered D-FF by switches

if Given that this circuit implements Positive Edge Triggered D-FF so What is the purpose of the switches S2 and S4? Hwo can i know what is the kind of S2 and what is the kind of S4 (P or N)?

• Homework? Good luck. Aug 9, 2016 at 20:30
• No.. i just want understand what is the purpose of S2 and S4.. Aug 9, 2016 at 20:31
• So what do you think? What will happen when they are closed? (BTW, I have never seen such a description of DFF.. it's rather..interesting) Aug 9, 2016 at 20:31
• D pass through.. i think that S1 is P and S4 is P. but so, what is the purpose of S2 and S4? Aug 9, 2016 at 20:33
• They short the out of the cascaded inverters to their input. Which, as far as I understand is supposed to emulate a one bit memory. Aug 9, 2016 at 20:34

A flip flop is two opposite phase latches back to back.

A latch consists (in this case) of a back to back inverter. To write into a latch you must overcome the feedback inverter (trying to write old value) with the input inverter which is driving the initial bitnode. One solution to this problem is to cut off the feedback inverter whenever the latch is transparent.

This is the purpose of the switches S2/S4: they prevent the second inverter in each chain from writing back to the input, while the latches are open.

This prevents contention, speeds up the latch, and reduces power consumption. Very common in VLSI. It also removes the need to size the input inverter stronger than the feedback inverter.

Opposite phase is the key word which helps you decide on what type of switch to use.

For a positive edge flip flop, the second latch must OPEN when the clock goes high.

Consider the situations:

CLK high: master latch closed, slave latch opened => S1=off,S2=on,S3=on,S4=off

CLK low : master latch open, slave latch closed => S1=on,S2=off,S3=off,S4=on


From here it easy to see that:

S1 = PMOS
S2 = NMOS
S3 = NMOS
S4 = PMOS


Although typically the switches S1/S3 would be transmission gates. And S2/S4 would be tri-state inverters built into the feedback inverters of each latch.

EDIT

Added a picture. Green circle arrow shows feedback. Red means switch is off. Blue shows where the output data comes from.

So, when clock is low the data is stored in the master latch.
When clock goes high, the master latch is cut off from D. Simultaneously the data from the master latch passes through the slave latch. So, rising-edge FF.

• So for what i need the chain of the NOT's? Aug 9, 2016 at 21:34
• That's the memory element. When the switches S2 or S4 are closed, the back to back inverters hold their value without any input given. Without these you would not be able to store your bit. Consider the first node Q @ a logical 1. This inverted makes a 0. Now this is inverted and fed back into Q to sustain the original logical '1'. Thus, memory is formed. Aug 9, 2016 at 21:37
• When S2 is closed (for example) ,so the value that pass through S2 is not equal to the value that pass Through the chain NOT's? Aug 9, 2016 at 21:43
• @Mathmatic: I honestly don't even understand your question. When S2 is closed then there is no feedback from the second inverter in the master latch to the input. So, whatever you put in D passes through S1 and shows up in the latch. If S2 was not there, the feedback inverter and the input driver would "fight" when writing a new value. For it to work properly, the input driver needs to be stronger than the feedback inverter. Otherwise it will never "flip the bit". Aug 9, 2016 at 21:45
• Can you explain it: "When S2 is closed then there is no feedback from the second inverter in the master latch to the input. " ? [why it so?] Aug 9, 2016 at 21:48