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I'm designing a battery-powered radio-linked sensor device which requires a long lifetime. Due to the project requirements I have very little onboard energy to work with; a single coin cell is the likely source and the lifetime requirement is at least a week.

My primary power savings will come from placing the device into a deep sleep mode and waking it with a timer every ten or so minutes to take a reading and transmit it. This means that for only 0.5% of the time is the device drawing any significant power; during the sleep state the consumption will be in the units of microamps at most.

The proposed process is as follows:

  1. MCU is powered on.
  2. The sensor is powered on by the MCU and a one-second grace time is given. The MCU is placed into a sleep state until the grace period elapses.
  3. The MCU communicates with the device via I2C or SPI and gets a reading.
  4. The sensor is powered off by the MCU.
  5. The transmitter circuitry is powered on by the MCU.
  6. The reading is transmitted.
  7. The transmitter circuitry is powered off by the MCU.
  8. The MCU triggers an external low-power (nA range) timer device which is configured to delay for approximately ten minutes.
  9. The MCU puts itself in power-down mode to conserve power.
  10. The external timer device triggers a pulse to a GPIO pin, which raises a waking interrupt in the MCU, returning us to step 1.

The ATtiny44A has multiple clock modes (section 6.2): an internal calibrated 8MHz clock, a low-precision internal 128kHz clock, and support for external clock sources and crystals. These can then be stepped down using the clock prescaler (see fig. 6-1 and section 6.3 for a description). I will be running the MCU at 3.3V.

As the processes performed by the MCU are not particularly time-critical, I'm trying to decide which of the following strategies are more optimal for low power consumption:

  • Use the internal calibrated 8MHz clock as-is with no prescaling, to minimise the time during which the MCU will be switched on. This has the benefit of speeding up the few calculations I'm doing on-chip and speeding up the IO with the sensor and transmitter devices. However, a potential downside is that other internal clocks are running at a higher frequency, and will remain running during the one-second grace period in step 2. My gut says that this is a poor choice since any power saved by quicker computation will be dwarfed by the one second of running the clock on idle.
  • Use the 128kHz low precision internal clock source. This increases computation and IO time, but may save power during the grace period.
  • Use the internal calibrated 8MHz clock with the prescaler set to 1/64, producing a 125kHz clock speed, emulating the low precision internal clock. I am unsure as to whether this is a useful option.
  • Use the internal calibrated 8MHz clock with the prescaler set to 1/256 (the maximum), producing a 31.25kHz clock speed. Again I'm unsure if this will save power.

Which of these, in the scenario described above, will result in the lowest power consumption?

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  • \$\begingroup\$ This depends on a lot of things; supply voltage, enabled peripherals, external chips (are those also powered down?), etc. The only way to get definitive answers for this is to build up your circuit and measure the power consumption of the various approaches. See also my answer to a similar question. \$\endgroup\$ – marcelm Aug 10 '16 at 12:26
  • \$\begingroup\$ @marcelm As I noted in my question, the supply voltage is 3.3V, and the external ICs (aside from the timer IC) are powered on only during the sensing period every ten minutes. \$\endgroup\$ – Polynomial Aug 10 '16 at 13:29
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Chapter 21 of the ATtiny44 datasheet has a lot of information about consumption vs. frequency and supply voltage.

A casual look indicates that the lowest clock frequency will lead to the lowest total consumption.

Table 21-2 contains some information about how much additional consumption you add from the various modules depending on frequency, again indicating that lower speed will net you lower consumption.

Depending on how fast you need the computation to be done you might be able to get away with the 128kHz clock speed.

I haven't looked at the I2C and SPI modules in detail but it is possible that they will not operate correctly at such a low frequency so you might consider bumping up the speed before doing any comms using those peripherals.

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  • \$\begingroup\$ The ATtiny44A is listed as fully synchronous, so I suspect the I2C and SPI modules should operate just fine as long as the peripherals are sufficiently resilient to slow clocks. The typical power consumption values in table 21-1 is useful as it gives some ballpark values at 3V. Section 21.2 looks ideal, though; I hadn't seen that before. 50uA looks typical for ~125kHz regardless of whether I go for the prescaling approach or the raw 128kHz clock. \$\endgroup\$ – Polynomial Aug 10 '16 at 13:38
  • \$\begingroup\$ Just found this, the ATtiny is a bit different from the ATmega in this respect: Chapter 14.3.6 Clock speed considerations Maximum frequency for SCL and SCK is fCK / 2. \$\endgroup\$ – Rob S Aug 10 '16 at 14:05
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There are a few options I see.

1) Run the device at a faster clock prescale setting when active, and switch to a lower prescale before going to sleep.

2) If the chip has a power-enable register for the peripherals, turn off the power enables for those peripherals when asleep. They will not draw power when disabled.

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