What is a flip flop?

Question

There seem to be a number of different definitions of flip-flops and latches out there, some of which are contradictory.

The Computer Science text book for the course I teach is probably the most confusing (in fact I have little faith in the book because it’s just plain wrong in several places).

I am comfortable with the workings of latches (SR, gated SR, gated D), and the difference between level triggered and edge triggered devices, at least in terms of logic gates and timing diagrams. However, I am still looking for a concise definition of a flip flop and of a latch.

This is what I believe so far:

“A flip flop is an edge triggered bi-stable device that can store 1 bit”.

“A latch is a level triggered bi-stable device that can store 1 bit.”

I’ve had a look at previous posts on this website about this and, as enlightening as they are, I am still looking for something definitive.

My current understanding, which I want to check, is in the diagrams below…

Side by side are what I understand are two implementations of a level triggered gated D latch.

Below these is a positive edge detector, at that brief moment when the NOT gate has not yet responded to the change input from low to high, namely the rising edge (red is 1 blue is 0).

In the last diagram, the edge detector has been fitted to a dated D latch and this is what makes it a flip-flop.

Is the last diagram really a flip flop, or is it still just a latch?

And why do we need the master slave version given, that this device is so much simpler?

Answer 1

I have been thinking about this definition a lot today.

As others pointed out, the exact meanings will vary. On top of that, you will probably see more people get this wrong, even on this site, than right. I don't care what wikipedia says!

But in general:

• A flip flop will change it's output state at most once per clock cycle.
• A latch will change its state as many times as the data transitions during its transparency window.

Additionally,

• A flip flop is very safe. Almost fool-proof. For this reason synthesis tools usually use flip flops. But, they are slower than a latch (and use more power).
• Latches are harder to use properly. But, they are faster than flip flops (and smaller). So, custom circuit designers will often "spread the flip flop" across their digital block (a latch on either end with opposite phase) to squeeze some extra picoseconds out of a bad timing arc. This is shown at the bottom of the post.

A flip flop is most typically characterized by a master-slave topology. This is two coupled (there can be logic between), opposite phase latches back to back (sometimes in industry called L1/L2).

This means a flip flop inherently consists of two memory elements: one to hold during the low cycle and one to hold during the high cycle.

A latch is just a single memory element (SR latch, D latch, JK latch). Just because you introduce a clock to gate flow of data into the memory element does not make it a flip flop, in my opinion (although it can make it act like one: i.e. more rising edge triggered). It just makes it transparent for a specific amount of time.

Shown below is a true flip flop create from two SR latches (notice opposite phase clocks).

And another true flip-flop (this is the most common style in VLSI) from two D-latches (transmission gate style). Again notice the opposite phase clocks:

If you pulse the clock to a latch quickly enough, it starts to resemble a flip flop behavior (pulse latch). This is common in high speed datapath design because of the lesser delay from D->Out and Clk->Out, in addition to the better setup time granted (hold time also must increase, small price to pay) by transparency through the duration of the pulse. Does this make it a flip flop? Not really, but it sure looks acts like one!

However, this is much harder to guarantee to work. You must check across all process corners (fast nmos, slow pmos, high wire cap, low wire r; as an example of one) and all voltages (low voltage causes problems) that the pulse from your edge detector remains wide enough to actually open the latch and allow data in.

For your specific question, as to why it is considered a pulse latch instead of a flip flop, it is because you truly only have a single level sensitive bit storage element. Even though the pulse is narrow, it does not form a lock-and-dam system which creates a flip flop.

Here is an article describing a very similar pulse latch to your inquiry. A pertinent quote: "If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing."

EDIT For some clarity I included a graphic of latch based design. There is a L1 latch and L2 latch with logic in between. This is a technique which can reduce delays, since a latch has lesser delay than a flip flop. The flip flop is "spread apart" and logic put in the middle. Now, you save a couple gate delays (compared to a flip flop on either end)!

Answer 2

Many people will refer to clocked devices as "flip flops" and non-clocked devices as latches. Back when I learned it, it was "clocked flip flops" and "flip flops". Either can be edge triggered.

There is enough ambiguity that when its important, rely on part numbersm data sheets, and timing diagrams,and not word descriptions.

Answer 3

Thanks to everyone who has answered my question. As expected, there is some disagreement. Unfortunately semantics are often more important than understanding when it comes to exams. If I need to argue with an exam board for incorrectly marking an A Level Computer Science student's exam paper (and I have done so in the past), I want to be in a strong position. I thought I'd share with you a couple of pages of the official A Level course text book.

The first diagram is an active low SR latch. The book calls it a flip-flop.

In the text, the book says "By using two flip-flops we can create a circuit called a D-Type flip-flop which uses a clock controlled circuit to control the output, delaying it by one clock pulse. The D stands for delay." This text seems to be referring to the master/slave configuration. The second diagram (figure 14.2) is labelled as a D-type flip-flop. It is actually an active high gated D latch.

Not very helpful!

I'm going to settle on "A flip flop is most typically characterized by a master-slave topology." as jbord39 has suggested, with the caveat that the term flip-flop is often used to mean an edge triggered latch, and sometimes just any sort of latch. I think this is where by book is coming from, albeit not getting there convincingly.

Thanks again to all.

Answer 4

A flip flop is different than a latch. They are both bi-stable circuits, but they are two different things in fact.

The latch has an enable pin and listens to the data input/inputs only when this pin is high. When it is low, the latch freezes and memorises its state. Now even you manipulate the inputs, it won't react.

The flip flop contains a clock pin instead, which reacts only at changing pulses (level shifts). Think of a square wave. The transient time between off and on;off and on is the time in which the circuit reacts to input signals. Only then is it available to change, not when the pin is stable and fully on.

Note the green lines represent the period it listens to input and the red lines the period when it doesn't. The latch allows input only during the periods shown by the uppermost red lines.

The stand-alone SR is not a feasible circuit in practice.

Credits to jbord39 for pointing out the mistake. Image taken from radio-elctronics.com and edited.

Answer 5

The terms as you use them in your question are 100% in line with what I've heard used in the context of analog IC design. Latches have a level-sensitive enable signal, whereas flip flops have edge-sensitive enable signals called 'clock'. I have noticed a few places online or in some books that seem to use the term flip flop for both types, which can make sense if you just think about the circuit state "flip flopping" between two stable points, but whenever designers are talking about a circuits where I work, latches are level sensitive and flip flops (or also commonly just "flops") are edge sensitive.

About your other question of whether to design a flip flop as a latch with an edge detector vs. a pair of master-slave latches. Either way can work, assuming there is enough delay in your edge detector. Latches will have some minimum amount of enable time. I suspect it's just harder to make a high speed flip flop using the edge detector technique, and the setup/hold time might vary more over process/voltage/temperature.

Answer 6

(Skip to the end if you want to know if the OP's last circuit is flip-flop or latch.)

In basic terms, a Flip-Flop is a arrangement of logic gates (or components) that allows the latching of 2 states along with a clock pin that enables these changes of states.

Now here is the difference between a Flip-flop and a latch. Latches are asynchronous while Flip-flops are synchronous.

• Asynchronous latches do not require an update pin, which would be commonly called the CLK (short for clock) pin in a flip-flop. All they care is if the inputs are in a specific state, either HIGH or LOW. When a certain combination of HIGHs and LOWs are instigated in the input, that is when the circuit decides to perform an action, and your desired outcome is returned "immediately". There are 4 possible actions in a latch.

  1. Do nothing
  2. Set Q to HIGH
  3. Set Q to LOW
  4. The invalid state (supposedly invert the value of Q)

  Note that Q' is dependent on Q.

An example is the SR latch which demonstrates all 4 possible actions a latch can do:

1. When S is LOW and R is LOW, nothing changes.
2. When S is HIGH and R is LOW, Q is set to HIGH.
3. When S is LOW and R is HIGH, Q is set to LOW.
4. When S is HIGH and R is HIGH, Q is inverted, at a "unpredictably" fast rate. This state is invalid.

• Synchronous flip-flops allow you to set a value to data pins. This means that it only cares about what these pins's state are. However the circuit doesn't decide to do any action to the output yet. You have the CLK pin as mentioned above. When the CLK pin changes state (either from LOW to HIGH, vice-versa or even both), the data pins are "captured" and the flip-flop performs an action based on the combination of HIGHs and LOWs of the data captured from the data pins. There are two actions for the CLK pin.

1. Do nothing
2. "Capture" data from the data pins and perform an action on the output based on values of data pins at that specific moment of time.

Again there are 4 possible actions the circuit can do on the output.

1. Do nothing
2. Set Q to HIGH
3. Set Q to LOW
4. Invert the value of Q (now it's valid because it only does it once)

THIS IS NOT A FLIP-FLOP:

But why you may ask? That E pin is not a clock pin. Clock pins let the circuit analyse the information from the data pins ONCE where that information gets sent as instructions to perform specific actions on the output. However enable pins like this one lets the circuit analyse the information from the data pins as long as it is held high and is constantly setting the values of the output. Thus it is a latch. (Thx to jbord39 for pointing out my mistake).

So the Flip-flop is like a latch, except you need an extra "confirmation" step, which is the CLK pin.

So is that last circuit of the OP's question a flip-flop? Try holding the C on high and see if the output changes when you change the value of D. If the output changes, it should be called enable instead and is a latch. But if the output doesn't change (in which that's the case), then it's a flip-flop.

Images are sourced from Wikipedia.