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FSK Modulation in VHDL

Hello, I have a VHDL block that performs FSK modulation. It looks like this

enter image description here

The operation of the VHDL block goes like this. Fsk_data selects Fsk_u or Fsk_l depending upon its bit value( either 0 or 1). The Logik block decides which bit of fsk_data to be used to set this multiplexer. What I need to do is to implement the counter function for this Logik block that increases with every clock cycle and when reached the maximum value will start again with zero.

The architecture of my VHDL code is as follows:

signal cnt_s    : std_logic_vector(21 downto 0);
signal temp_s   : std_logic_vector(7 downto 0);
begin

process(reset_n_i, clk_128meg_i,cnt_s)

begin

if(reset_n_i='0') then
    cnt_s <= (others=>'0');
elsif (clk_128meg_i'event and clk_128meg_i ='1') then
    if(enable_i='1') then
        cnt_s <= std_logic_vector(unsigned(cnt_s)+1);

But, after this I don't have any idea how to proceed. My point is that I need to point the next address of the fsk_data register using the cnt_s (cnt_s acts as a pointer here) in order to select either fsk_u or fsk_l. I need to know whether my point is right. Help is appreciated in proceeding this code.

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If I am not wrong, this is my idea. You want to change your data stream on base of fsk_data and use counter for selection purpose. Let say you provide the fsk_data to logik. Inside your logik you have counter that select the pins of fsk_data which is 22 bit wide. Use counter of 5 bit & max value equivalent to 21 and fsk_data(counter_value) to point fsk_data respective bit. Use that value as selection line for mux. Try to run the counter negative edge (not gate with clk) to make it advance for output FF.

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  • \$\begingroup\$ thanks Abdullah. I did the same and got the output as expected. \$\endgroup\$ – Vijay Karthik Aug 11 '16 at 15:03

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