FSK Modulation in VHDL
Hello, I have a VHDL block that performs FSK modulation. It looks like this
The operation of the VHDL block goes like this. Fsk_data selects
Fsk_l depending upon its bit value( either
Logik block decides which bit of
fsk_data to be used to set this multiplexer. What I need to do is to implement the counter function for this
Logik block that increases with every clock cycle and when reached the maximum value will start again with zero.
The architecture of my VHDL code is as follows:
signal cnt_s : std_logic_vector(21 downto 0); signal temp_s : std_logic_vector(7 downto 0); begin process(reset_n_i, clk_128meg_i,cnt_s) begin if(reset_n_i='0') then cnt_s <= (others=>'0'); elsif (clk_128meg_i'event and clk_128meg_i ='1') then if(enable_i='1') then cnt_s <= std_logic_vector(unsigned(cnt_s)+1);
But, after this I don't have any idea how to proceed. My point is that I need to point the next address of the
fsk_data register using the
cnt_s acts as a pointer here) in order to select either
fsk_l. I need to know whether my point is right. Help is appreciated in proceeding this code.