It is given in "Ned Mohan Power electronics converters applications and design" that, "sinusoidal PWM output's instantaneous average (over one time period of carrier wave) is same as the fundamental frequency component in the signal." I am unable to think how, instantaneous average is related to only fundamental frequency component as, instantaneous average may include any slow varying (low frequency signal's contribution) components, as high frequency ones near by switching frequency get zeroed in a time period. 'mf' frequency modulation index when chosen appropriately, odd such that output becomes odd symmetric (only sine components) and half wave symmetric (only odd harmonic components) too, 3rd harmonic may interfere. How can we make sure that output doesn't contain 3rd harmonic, that too if contains, would be less compared with fundamental one ? Please help me understanding this..
To complement Andy aka...
The quote in question.
sinusoidal PWM output's instantaneous average (over one time period of carrier wave) is same as the fundamental frequency component in the signal
Take a 10V pk sine wave and take a PWM signal that toggles between +15V and -15V.
At zero degrees (or the equivalent timebase): a sinwave will have an amplitude of ... 0. Now take an associated PWM that would be used to synthesis a sinewave at this point in time. At this point the PWM duty will be 50% -> 0V
Now take 90deg (or the equivalent timebase) the sinewave would be at its peak, a peak of +10V. At this instance, the PWM (concidering one period) duty would be 83.333...% and this would have an average of +10V
"3rd harmonic may interfere."
We know from Information Theory and Shannon's Law that signal being sampled cannot exceed 1/2 of the sampling rate. Now we can see from the low pass filter response of the PWM output, has a noise factor on the signal depending on these ratios of frequencies and the attenuation slope.
This tradeoff means we need a specification for signal bandwidth and thus Step Load response time in a SMPS closed loop or order to validate the switching frequency to loop bandwidth requirements.
- The Loop bandwidth is often chosen less than 1/3 of switching frequency which is like saying the 3rd harmonic starts to cause aliasing or interference noise with the PWM in your question.
- With 6dB per octave filtering that implies the 3rd harmonic signal level is down 12dB for a signal at the loop bandwidth frequency. This in turn implies a certain amount of jitter on the PWM filtered signal and thus noise level in a supply.
This is not the only source of ripple as the ESR of components is another limiting factor with Ip-p*ESR ripple in caps.
Maybe this picture will help: -
There are three waveforms: -
- Basic sinewave (red)
- Triangle wave at PWM frequency (one triangle occurs in one switching cycle) in green
- PWM waveform at bottom of picture (blue)
If you look at the PWM waveform (blue) and averaged the high/low content in each switching cycle, you would get varying numerical values that followed the basic waveform of the sine wave. Switching cycle: -
So, for the 1st cycle, the average is about 25% and, for the second cycle, the average is about 60%. You don't need a calculator to estimate this, just use your eyes and ask yourself how much of the waveform is "high" in a particular switching cycle then move onto the next one.
It's got nothing to do with frequency modulation or harmonics, just averaging. Averaging can be done by basic resistor, inductor and capacitor combinations aka "low pass filters".