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I have been told that when laying out a PCB to keep all the polygon pours uniform on each layer. So, for example, in a corner of the PCB, you do not want the pour on one layer slightly offset relative to the other, like this:

Screenshot of PCB polygon

The red layer is the top layer, brown is the second, blue is the third.

I have been told this is bad, but why? No one can give me a reasonable answer, and I don't want to do something just because someone told me to do it this way, I would like to understand what issues can come up with this sort of design.

Or is it just down to aesthetics?

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  • \$\begingroup\$ I think, if there are no components on the edges that carry varying currents, it is better to create some offset so that after the production of the PCB, these layers can be seen by eye if put into some light \$\endgroup\$ Aug 11 '16 at 7:27
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    \$\begingroup\$ It is a radiated emissions issue. There used to be a school of thought that the GND plane should be closest to edge, and all other planes should be pulled back from GND. Nowadays, the thinking is that makes radiated emissions worse, and the best thing is to keep the plane edges exactly the same. I always follow the newer thinking, but I have not seen hard evidence on this issue. \$\endgroup\$
    – mkeith
    Aug 11 '16 at 7:42
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    \$\begingroup\$ It looks as if you do not care about making it neat and tidy. \$\endgroup\$
    – CL.
    Aug 11 '16 at 7:46
  • \$\begingroup\$ @mkeith I was thinking this was the reason. \$\endgroup\$ Aug 11 '16 at 11:04
  • \$\begingroup\$ That tiny difference of 0.1 mm isn't going to have any RE/RS effect on anything that isn't high speed enough to warrant different technologies. Keep them squared up and if you're in a frequency range where that somehow causes problems, I suspect you may be better off with a via fence or edge plating \$\endgroup\$ Jul 9 at 4:01

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