4
\$\begingroup\$

I have been told that when laying out a PCB to keep all the polygon pours uniform on each layer. So, for example, in a corner of the PCB, you do not want the pour on one layer slightly offset relative to the other, like this:

Screenshot of PCB polygon

The red layer is the top layer, brown is the second, blue is the third.

I have been told this is bad, but why? No one can give me a reasonable answer, and I don't want to do something just because someone told me to do it this way, I would like to understand what issues can come up with this sort of design.

Or is it just down to aesthetics?

\$\endgroup\$
6
  • \$\begingroup\$ I think, if there are no components on the edges that carry varying currents, it is better to create some offset so that after the production of the PCB, these layers can be seen by eye if put into some light \$\endgroup\$ Commented Aug 11, 2016 at 7:27
  • 5
    \$\begingroup\$ It is a radiated emissions issue. There used to be a school of thought that the GND plane should be closest to edge, and all other planes should be pulled back from GND. Nowadays, the thinking is that makes radiated emissions worse, and the best thing is to keep the plane edges exactly the same. I always follow the newer thinking, but I have not seen hard evidence on this issue. \$\endgroup\$
    – user57037
    Commented Aug 11, 2016 at 7:42
  • 1
    \$\begingroup\$ It looks as if you do not care about making it neat and tidy. \$\endgroup\$
    – CL.
    Commented Aug 11, 2016 at 7:46
  • \$\begingroup\$ @mkeith I was thinking this was the reason. \$\endgroup\$
    – ofithch79
    Commented Aug 11, 2016 at 11:04
  • \$\begingroup\$ That tiny difference of 0.1 mm isn't going to have any RE/RS effect on anything that isn't high speed enough to warrant different technologies. Keep them squared up and if you're in a frequency range where that somehow causes problems, I suspect you may be better off with a via fence or edge plating \$\endgroup\$ Commented Jul 9, 2021 at 4:01

1 Answer 1

3
\$\begingroup\$

You know, I think if you ask different people from different fields (RF, analog, digital, PE, EMS's/PCBA manufactures) you'll get different answers. People working in higher frequency may quote EMI/EMC issues, and others may quote manufacturing related issues.

Like with any facet of engineering, there is probably a scenario that exists where the advise they give is only useful to them because of the environment or design conditions they find themselves in. It's not a particularly helpful answer, but, unfortunately it's true.

BUT, no matter what field you're in and if you are making PCBs, they have to be manufacturable. So, a couple of reasons PCB shops want copper pulled away from the edge are:

  • Corrosion - having copper come to the edge exposes it to oxygen, which can then kick start oxidation.. you can imagine the problems if all your plane layers are oxidising..

  • Short Circuit - kind of a specific sub point to the above, but, oxidation can cause tracking via dendrite formation, which then could cause a short on the board edge between layers. For instance, I attached an image showing this not on the board edge, but, on an external layer between pads. enter image description here

  • Safety - Not a PCB fab reason but, having copper all the way to the edge also leaves the chance for something/someone to interact with the circuit, increasing chance of electrical shock.

There isn't one answer here where you'll leave this conversation going "okay, that provided the entire picture and now I know". It's more of a collection of answers given the field and environment you work within. But, like I said, the board needs to be manufacturable so hopefully the first two manufacturing related answers gave you some points to start looking into.

Here are a couple of links you can look into that will help kick start your investigation:

\$\endgroup\$
3
  • 1
    \$\begingroup\$ Also, there is a Gerber file convention that copper that is drawn to and over an edge cut indicates a plated edge, and the edge cuts layer is split in two different processing steps (before/after plating). Of course that can be worked around easily by the fab house, but it is a manual step. \$\endgroup\$ Commented Feb 13, 2023 at 18:47
  • \$\begingroup\$ Interesting addition Simon, I didn't know that convention existed. The only "plated edges" I've come across are castellated holes where I just note them within our Fab drawing layer. \$\endgroup\$ Commented Feb 13, 2023 at 20:23
  • \$\begingroup\$ this is mostly used for routed slots, like the long holes required for barrel jacks. \$\endgroup\$ Commented Feb 13, 2023 at 20:48

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.