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We know that in multi-cycle implementation of a MIPS processor, the R type instruction takes 4 cycles.

However, in the pipeline implementation of MIPS, for R type instructions, 4th stage (MEM) is present but nothing significant happens (during that stage). The actual register file write-back occurs in the 5th cycle (WB).

Why doesn't the write back happen in 4th cycle itself (for pipeline) ?

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Why doesn't the write back happen in 4th cycle itself (for pipeline) ?

Simply because that's not the function of the 4th cycle. Think of the pipelining as a series of buckets. Each bucket has a specific role. Water is poured into the first bucket. From the first into the second. From the second into the third, etc. When the water is in each bucket a specific thing is done to it (if needed). Only when it reaches the 5th bucket will the operation associated with the 5th bucket be performed on it.

In more CPU-like terms, each phase of the pipeline is a separate sub-circuit with dedicated operations. The 5th phase deals with the write-back to registers. The 4th doesn't You can't do it in the 4th phase because that sub-circuit doesn't have the ability to write to a register, only to memory.

Also you can't "skip forward" from the 3rd phase to the 5th phase since the 5th phase is in use by the previous instruction in the pipeline.

This image should clarify:

enter image description here

If instruction 2 skipped direct from ALU to Reg it would collide with the previous instruction if that went ALU -> DM -> Reg since both Reg operations would be occurring at the same time in the same physical circuit (at clock cycle CC5).

One optimization that it can (and does) do though is to send data back down the pipeline so instead of writing to, say, register $4 and then reading from register $4 immediately afterwards it just passes the data back to where it would be read from $4 to save time. This is called Data Bypassing and is detailed in section 2.6 of the MIPS M4K manual.

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