No there is nothing majorly wrong with the layout, it turns out that the ethernet transformer was out of spec by 0.2dB on Insertion loss, when paired with the PHY IC we are using.


Is there anything noticeably wrong with the PCB routing of the gigabit ethernet?

Gigabit Ethernet has many design constraints, due to the layout of components on the PCB it is at times impossible to follow all the design rules. This design is required to perform Gigabit speeds, and feed a POE supply.

It must also pass FCC EMC/EMI and ESD testing.

I have read through almost all application notes available (TI, Intel..etc). I have, to the best of my knowledge, followed them as best I can. Traces are routed as diff pairs, and with the best possible spacing to prevent cross talk. Minimum use of vias/stubs of 2 per a segment. They are symmetrical as possible, and post magnetics each pair is matched to within 1.25mm, pre magnetics they are matched to within 2mm. Traces are routed on the bottom layer to avoid crossing multiple power planes as a reference.

However this design presents some challenges which I am too inexperienced to assess. Ie When do you choose to violate design rules, and to what extent can you get away with it.


  1. The RJ45 and Magnetics have to be positioned as they are. The traces from the RJ45 to the Magnetics are length matched to within 2mm and are all laid as differential pairs. However is is a bit of a muddle - will this cause an issue with the GBE performance?
  2. Due to constraints the magnetics has two center tap traces laid underneath it (For the POE) - would this become an EMI issue? (Application notes suggest avoiding the area below magnetics)
  3. Post magnetics there are two features to be wary of - a crystal oscillator, and a transformer (in a cutout) which may add noise to the signal.How can this be avoided?
  4. Are the VIAs/Stubs at the phy end laid out in an acceptable manner?

Are there and obvious shortcomings of this layout that I am missing? GBE and POE routing

RJ45 to Magnetics


2 Answers 2


Things that spring to mind:

  • usually, you'd model your PCB trace as transmission line that has exactly the same characteristics on the top, as on the bottom layer. As such, it doesn't make much of a difference where on the length of a trace you put the via; so instead of having these "looking like boobies" vias right next to each other, I'd just offset them enough to keep them in the middle of your trace
  • R51, C5 could as well be on Top Layer
  • I don't know the frequencies of your xtal or CPU, but chances are that the 125 Mbaud of Gigabit ethernet won't be much impressed :) however, if you're nervous about coupling, you might want to consider the classical star-like multiple ground-plane architecture. I don't think this'll be necessary here – Gigabit Ethernet Network PHYs aren't exactly bleeding edge in 2016, so even with some interference, they should work.
  • just looking at the part of the layout I see, I'd say it might be easier to route if you just rotated the PHY by 90° – but that might break down the moment the complexity on the "processor side" of the phy comes into play.
  • I think your RJ45-magnetics layout is OK; I'd probably been lazy and just routed the two diff pairs that are at the right half of the transformer "down" from the connector's pins, and the left half "up"; but that wouldn't have saved you from the one pair that crosses the other if you're supposed to access the magnetic's pads only from one side (unless you fit two traces between adjacent RJ45 pins...) . Topology is not always your friend :/

Notice: 1GE has a baudrate of 125 MBaud, i.e. even if considering the first two sidelobes, you really shouldn't be worried about frequencies above 375 MHz. With FR4 (with specific epsilon), and a lot of laziness approaching formulas, the wavelength of that frequency is roughly \$\frac15 \frac{c_0}{375\text{ MHz}}= \frac 15 \frac {3\cdot 10^8 \frac{\text m}{\text s}}{3.75 \cdot 10^8\frac1{\text s}}\approx \frac4{15}\approx 0.27\text{ m}=270\text{ mm}\$, so a 2mm trace length difference is but 2.7° phase error ... I think you'll be fine, even with a bit of unelegant routing.

  • \$\begingroup\$ +"dem boobie via" I will space a bit better + R51, C5 are obstructed on the top layer + Its a low Mhz xtal, I was thinking of adding a slot in the ground plan and a ring in the gnd on the layer its on around the xtal to get it deeding back towards the uProcessor + 90deg PHY is out the question, the only possible rotation is the magnetics at 45d egree \$\endgroup\$ Commented Aug 14, 2016 at 15:21
  • \$\begingroup\$ + The RJ45 > Mag layout can be done better reducing length, but then I get traces running parallel on top of each other (on bottom and top layers) and i'm not sure if that is a good idea? \$\endgroup\$ Commented Aug 14, 2016 at 15:25
  • \$\begingroup\$ Also on "dem boobie vias" the application notes suggest placing vias as close to the pins as possible. \$\endgroup\$ Commented Aug 14, 2016 at 15:32
  • \$\begingroup\$ @KieranDuggan The reason is because of the return current. When you move from top to bottom, the return current needs to change reference plane from 2nd to 3rd. What happens is it finds the closest capacitor to do that. This creates a large loop area, if the capacitors are farther away i.e. more emissions, impedance discontinuities etc. \$\endgroup\$
    – user110971
    Commented Aug 14, 2016 at 20:18

I advocate single layer routing for any high speed signals.

The GigE tracks are referenced to ground at the magnetics side, but referenced to the power layer at the PHY side. To avoid using stitching capacitors you could move the power at the magnetics (connected clearly to some decouplers) to layer 4 and simply route the GigE all on layer 1; with no vias, there will be no discontinuity but the reference layer would need to be solid all the way from the magnetics to the PHY which may need a bit of work.

That said, there is another advantage of single layer routing: the impedance of two different layers in an impedance controlled board will never match 100%. That means that even with stitching caps, there will be reflections (not huge but they will exist) at the layer change. On a typical PCB, the impedance of 2 different layers will be different by 10% or so, with a reflection coefficient of just over 9% assuming a perfect return path.

You could, alternatively, make the area on layer 2 ground where the vias and ethernet tracks exist on layer one, but you would still need stitching vias for the reference layer to change from layer 3 to layer 2.

I have taken your image to show where they would go:

Stitching via locations

That won't change the fact you will have some discontinuity, but it will keep it to a minimum. The stitching vias provide a short path between the reference layers; if they are not there, the return path will need to find the nearest point at which the return current meets - the further away that is (up to a certain limit), the larger the discontinuity.

In general, I try not not to put anything under the magnetics, but as your tracks are apparently shielded by the ground layer, I do not see a major issue with those.

  • \$\begingroup\$ + Due to the complexities of the power supplies the layer order and planes can not be adjusted :( + Ill add the stitching vias (they all those vias randomly around R22) \$\endgroup\$ Commented Aug 14, 2016 at 15:30
  • \$\begingroup\$ The traces under the magnetics are fed into a bridge rectifier and then through another transformer - im hoping this deals with any injected noise. \$\endgroup\$ Commented Aug 14, 2016 at 15:30
  • \$\begingroup\$ @KieranDuggan are you using the same ground reference for the output of the bridge rectifier as the output of the PoE transformer? Or are the grounds isolated? \$\endgroup\$ Commented May 25, 2023 at 17:25

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