# Why the drop across NMOS enhancement mode load is V_t when driver is off?

In the enhancement load NMOS inverter, why is the voltage drop across the Transistor $Q_1$ when $Q_2$ is off, is $V_t$ ?

When $V_{1}$ is low, the transistor $Q_1$ is off. For the transistor $Q_2$, the voltages $V_{ds}$ = $V_{gs}$, therefore the $V_{ds}$ > $V_{gs}$ - $V_t$ and the transistor $Q_2$ is in saturation. Now, it can be said that as no current flows through $Q_2$ and $Q_1$ (except negligible leakage currents) then from the equation:

$I_{ds}$ = $\frac{\beta_{gs}}2 (V_{gs}-V_{t})^2$

If $I_{ds}=0$ then $V_{gs}=V_{t}$.

Is this analysis correct? If it is, I want to know the physical process behind why this voltage drop exactly equals to $V_t$ occurs across $Q_2$ when no current flows through $Q_{2}$? Shouldn't the drop be just 0 for ideal switch?

It is important to understand that Q2 is in Saturation mode and not cut off mode, therefore some current flows through it (channel length modulation) which cannot be neglected. Because of the current flowing through the NMOS there is voltage drop even when Q1 is off. For Quantitative analysis we cannot ignore the current from NMOS in the saturation region.

This is a rather tricky question, its answer may easily vary between a few different options upon degrees of ideallity and other assumptions made.

Let's start from the ideal MOS model described by the equations you've written down.
Instead of equations I believe it's easier to solve the problem graphically on the I/V characteristic.

We have to find crossing between MOS I/V locus and the straight line I=0 which represents the open cirtuit applied by the "driver off" condition.

It is clear that any point on the segment $I=0$ and $0<V<V_\text{th}$ is solution, hence we cannot tell which will voltage be actually.

Sometimes dealing with ideal models is like this, those are simply not accurate enough to mimic actual world.

Now let's connect a voltmeter on source, it is indeed needed to check what's the voltage. It may be hi input impedance but let's assume it will draw a tiny but not zero current.

This is enough for the ideal MOS model to converge somewhere very close to Vth

And it's probably why this is the "correct" answer in many circumstances.

Nonetheless improving a little bit MOS model you can get different answers, in real life MOS there is a sub-threshold current which is probably much greater than the one taken by a good voltmeter.

In this case voltmeter would read a drop around 0V or at least somewhere in [0,Vth]

When Q1 is off, then the drain-source voltage of Q2 is zero and Vout equals Vdd. Q2 is off since Vgs = 0 < Vt. Of course assuming that there is no load at the output.

It is little bit difficult to understand because the transition between on and off requires that the transistor operates in the sub-threshold region and this is not covered by the simple square-law model.

A connection between drain and gate does not automatically imply that the transistor will always be saturation. The problem is that the equations you are using are derived under certain conditions and these equations can't be applied if any of these conditions are violated.

In particular it is assumed the transistor operates in a condition known as "strong inversion", which basically means that a channel has formed underneath the gate.

As a rule of thumb this condition is met if Vgs - Vt > 100mV. In your problem this condition can't be fulfilled. Consequently your transistor does not operate in strong inversion and is therefore also not in saturation (because the concept of saturation implies the presence of a channel).

To understand the transition between the on and off condition the operation in weak inversion is important. This region is governed by a different set of equations and I'm sure they'll be discussed in your textbook at a later point.